• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 1094 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS1227: Data flash erase times

Steven Aris26
Prodigy 210 points
Part Number: TMS570LS1227

Hi,

We've just come across an issue where we do not appear to be allowing sufficient time to erase one of the data flash banks.  We haven't seen this particular issue before, even though we've got a fair number of boards\processors that have been in use for, in some cases, years.

The TRM for the 1227 specifies that the erase time for the bank 7 flash is:

Min Nom Max Unit
-40C to 125C - 0.2 8 s
0C to 60C, for first 25 cycles 14 100 ms

I guess what we'd like to know is whether there is any more data available for the data flash erase times?  Perhaps some graphs or tables that show the effect of time and\or age on the erase times?  Especially as there seems to be a large difference between the '0C to 60C, for first 25 cycles' and the '-40 to 125C' timings.

Best regards,

Steve

  • 0
    TI__Guru**** 196856 points

    Hello Steve,

    We don't have more data to share.

    The erase time is worst case for a single sector when doing sector erase, or the whole bank if doing bank erase. In bank erase all the sectors are being erased at the same time so the time of the bank erase is equal to the time to erase the slowest sector.

    Erase time degrades with the number of write erase cycles. Sometimes during erase traps (an extra electron or hole stuck in the oxide lattice) are formed in the erase oxide. These traps make the next erase harder. Some of the traps will anneal with time and high temperature. TI has very conservatively specified the maximum erase time to account for a worst case scenario of 90,000 cycles at high temperature (where traps form most easily), with no time between write erase cycles (no time for traps to anneal), then with 10,000 write erase cycles at cold temperature (where erase pulses are least effective). The 8 second specification was set so that even the slowest to erase device would finish in these extreme conditions.

    In summary, the erase time increases primarily with the number of write erase cycles, and secondarily as the temperature decreases. Also, the maximum erase time varies greatly between devices as they near the 100,000 write erase cycle limit.