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TMS570LS3137: PBIST on CPU RAM Precondition

Kalyan Vagvala61
Expert 1075 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hello,

i have a question regarding the afterSTC() code generated by HALCOGEN version 4.7:

Below are the set of instructions from afterSTC(), why should we call _coreDisableRamEcc_() before CPU RAM TEST? I did search TRM but couldn't fine any specific information. can you please help me to undestand this? 

/* Disable RAM ECC before doing PBIST for Main RAM */
_coreDisableRamEcc_();

/* Run PBIST on CPU RAM.
* The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
* The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
* device datasheet.
*/
pbistRun(0x08300020U, /* ESRAM Single Port PBIST */
(uint32)PBIST_March13N_SP);

Thanks,

Kalyan

  • 0
    TI__Mastermind 49120 points

    Kalyan,

    It is not required to disable the ECC checking on RAM accesses before you start the PBIST run on CPU RAM. The PBIST engine also programs the ECC locations of the RAM along with the data writes. Also, if you keep the code sequence generated by HALCoGen, there should be no RAM accesses between this instruction and the memory initialization, where the RAM is zero'ed along with the correct ECC.

    Regards, Sunil