TMS570LC4357: EMIF Self testing

Hello Shivam,

Please make sure the setup time, strobe time, and hold time meet the requirements defined in datasheets (TMS570 and SRAM datasheet).

If cache is enabled, please configure the 0x6000_0000 memory MPU region as write-through instead of write-back (MPU tab in HALCoGen).

If the memory is 16 bit, address 0 of the memory should be connected to EMIF BA[1], and address 1 is connected to EMIF address[0].

Hi Wang,

I have tried the following things:

#define Chip_Select_2 ((uint32 *)0x60000000U)

int count= 1;
uint8* address = Chip_Select_2;
while(1)
{
if(address < 0x63ffffff)
{
*address = count;
count++;
address++;
}
}

here, I am trying to increment the address value by sending the byte, and i have observed that:

For,

Address Line A0: it remain as 1

Address Line A1: it toggles after 8 bytes are transmitted

                            ie. for address from 0x60000000 - 0x60000007 it remains 0 and after that goes to 1 for next 8 count

Address Line A2: it toggles after 16 bytes are transmitted

                            i.e. address from 0x60000000 - 0x6000000E it remains 0 and after that 1 for next 16 count

Address Line A3: it toggles after 24 bytes are transmitted

                            i.e. address from 0x60000000 - 0x60000016 it remains 0 and after that 1 for next 24 count

and so on...

is it expectable the same for the Emif? Does my observations are correct?

Please assist me.

Regards,

Shivam Kakad

Thanks Wang for the detail description.

Can you please tell me the address mapping for the EMIF.

How the mapping of this a0 to a21 lines has been done for the chip select 2, and whether that is same for the other chip selects and sdram as well?

As well as for the data mapping i would be keen to know.

Please provide the document if any.

Regards,

Shivam Kakad

Hi Wang,

As per the description you provided i could not able to get the results.

for A0 it is continuously staying at 1,

for A1 it change the status at

07->0F->17->1F->27->2F->37->3F->...

for A2 it change the status at

0F->1F->2F->3F->4F->5F->...

for A3 it change the status at

17->37->57->97->B7->...

for A4 it change the status at

37->77->B7->...

Why is it showing such status.

How the logical and functional mapping is there for the address line?

Can you please provide me the document for the address mapping of it, so that i can relate to it?

Thanks in advance.

Shivam Kakad

Hello Shivam,

Is there a memory attached to EMIF? After you write data to EMIF memory, is the data is correct location of the EMIF memory? Please refer to Interfacing to Asynchronous Memory in EMIF chapter of TRM.

Hi Wang,

No device is connected to EMIF and would like to test EMIF module without connecting any to it. So, help us in testing them and provide us the details as requested by Shivam.

Hi Wang,

Can you please provide us the complete bit mapping details of address and data lines, so that it will be clearer for us?
We are seeing A0 to 1 and do you see any reason or anything to be checked further on why it is setting it up?