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TMS570 how to write your own interrupt handler despite Halcogen

Other Parts Discussed in Thread: HALCOGEN

Hi,

the Halcogen generated interrupt handlers are not fit for our purpose.  

My question now is: how can you write your own interrupt handler while still using halcogen?  

Changing the name in the "VIM RAM" tab does not help; it simply changes the name of the generated interrupt handler.   Or is it not possible doing that while still using halcogen?   Not using it would be no problem either; so far it has rather delayed than helped us.   Please note that changing halcogen generated files by hand after code generation is no option.

Regards,

  • Hello Hagen,

    You are right. Changing the name in the "VIM RAM" tab is only to change the name of the generated interrupt handler. It doesn't generate a empty ISR with the new name.

    The HALCOGen generated ISR doesn't do data processing, it checked the INT flag register, then branches to notification function. Please add your code to the notification function.

    For example, the HALCOGen generated ISR checks gioREG->OFF1, then jump to gioNotification(gioPORTA, offset) which is located in notification.c

    void gioHighLevelInterrupt(void)
    {
        uint32 offset = gioREG->OFF1;

    /* USER CODE BEGIN (14) */
    /* USER CODE END */
     
     if (offset != 0U)
     {
            offset = offset - 1U;
            gioNotification(gioPORTA, offset);
     }
     
    /* USER CODE BEGIN (15) */
    /* USER CODE END */

    }

     

  • Hi,

    you are wrong, the interrupt handler does data processing in case of the SCI.   Using the notification is no solution because the overhead through the interrupt code in sci.c and then the notification and having to call sci_receive() again for every byte received is not acceptable.

    We disabled the interrupt in halcogen now and we are using the vim_channel_map() and vim_enable_interrupt() functions.   That works without all the halcogen overhead and we can still use the halcogen code that works around all the faults (errata) in this processor that would be difficult to find otherwise.

    Regards,