TMS570LS1227: TMS570 SPI usage question

Hagen,

SPI is a synchronous communication. The serial clock SPICLK is required. The SPICLK is generated by master. SPIENA is optional which is used to enable a slave SPI to delay the communication.

If you only transmit data to one device, you can use two pins: SPICLK and SPISIMO. SPICLK is a MUST.

Hi,

ok, you obviously did not read my post it so I have to repeat it: WE ARE USING THE SPI OUTPUT TO GENERATE A UART SIGNAL.  WE DO NOT USE ANOTHER SPI ON THE RECEIVING SIDE.  So we still have to enable the hardware clock output pin in order to get a signal on MOSI?

Regards,

Hi Hagen,

If you want to use SOMI as SPI functional, the SPI clk has to be configured as functional even it is not connected to another device. If polarity and phase are 0, the SIMO data is output on the rising edge of SPICLK, and input data is latched on the falling edge of SPICLK. If the SPICLK is not enabled, or you configure this pin as GIO, you will not be able to see data on SIMO pin.

If you use SIMO pin as GIO, and use this GIO as UART signal, you don't need to configure SPICLK as functional. 

"If the SPICLK is not enabled, or you configure this pin as GIO, you will not be able to see data on SIMO pin."

Why?   What is the reason for stopping the output signal when the clock is not routed to the outside?   Can you explain to me why ti decided to waste silicon space to reduce the functionality of an ic that is suffering already from using pretty much half of the pins on supply and otherwise useless adc input only pins even more???   What were the designers thinking???

"If you use SIMO pin as GIO, and use this GIO as UART signal, you don't need to configure SPICLK as functional. "

Are you seriously suggesting I am bit-banging a GIO to get a UART output as a workaround on a $20 IC???

Why is it that we are running into problems left, right and centre with the hardware and software of ti all the time whereas we do not see that with other manufacturers products?   I will definitely have a serious talk with our customer(who insisted on ti originally).

But thank you for your post, it confirmed what we feared already.   I have to double check but I think if MISO isn't routed to the outside the SPI stops too.   So we need 3 pins for one output signal when using ti :-(

Hello Hagen,

I am sorry for my confused words.  You don't need to route SPICLK to the outside, you only need to configure SPICLK as SPI functional signal.

May I know why you use SPI UART. TI has an example to use N2HET as UART.

Hi,

ok, I have to double check on that one and check how the pin / gio select is internally connected.   But I am pretty sure when I did not have the signal routed to the outside pin (GIO selected) the SPI would not start transmitting.   Whereas when the pin was selected as funtional SPI pin the SPI worked.  Cannot test it at the moment but will repeat it asap.

We have two coprocessors in the system via two isolation barriers that requires a UART each.   Also two external RS232 interfaces (one output only and one both ways).   And another TI IC that requires UART communication as well.    So that makes 5 in total.  Both HETs are used as UARTs already, having two UARTs running in one HET seems to be impossible due to processing time constraints (I think code uses 34 slots; with 32 it would work).   Adding the output only UART into one of the source files (that I believe you provided)  would be possible but I do not see us writing HET microcode as an option (Motorola did that microcode timer concept about 30 years ago and failed, so I'm surprised that TI is trying it again).  So the SPI as a simple output only UART seemed like a good idea at the time and we had it tested on an EVM (but with output pins MOSI, MISOI, CLK active).  We will have to change some pins and modify the PCB, not nice but it doesn't seem we have a choice.

Regards,