• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 29 subscribers
  • Views 681 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LC4357: How to invalidate Flash prefetch buffer/cache?

Etienne Alepins
Intellectual 775 points
Part Number: TMS570LC4357

Hi,

TMS570LC4357 TRM Rev. A Flash chapter slightly describes the prefetch mode. We know how to disable the feature (i.e. by setting FRDCNTL[PFUENB, PFUENA]=0). However, major aspects of that feature are not described:

1) Once prefetch mode disabled, is the prefetch buffer/cache still used when answering reads?

1.1) If so, how can we invalidate it's content to make sure there is no more hits in the Flash buffer/cache?

2) What is the width of a Flash cache line? (in bytes) Same for ports A and B?

3) What is the depth of that Flash cache? TRM §7.7.2.1 "Address Tag Register Test Mode: DIAGMODE = 5" mentions 2 for port A and 4 for port B.

3.1) How come it is different since each port covers the same amount of data? (2Mb)

4) What is the replacement policy of Flash cache lines? Round-robin?

All these answers should normally have been found in the TRM...

Thanks.

  • 0
    TI__Mastermind 49120 points

    Hi,

    Please see comments in your note below. I have replaced the word "cache" with "flash prefetch buffer" from this discussion to avoid confusion between the CPU cache and the flash prefetch buffer.

    1) Once prefetch mode disabled, is the prefetch buffer still used when answering reads?

    >> The prefetch buffer is not used for reads once it is disabled using the PFUENA/B bits.

    1.1) If so, how can we invalidate it's content to make sure there is no more hits in the Flash prefetch buffer?

    >> This is not necessary, as the prefetch buffer is not used when disabled.

    2) What is the width of a Flash prefetch buffer line? (in bytes) Same for ports A and B?

    >> The flash prefetch buffer is 32 bytes wide for both ports A and B.

    3) What is the depth of that Flash prefetch buffer? TRM §7.7.2.1 "Address Tag Register Test Mode: DIAGMODE = 5" mentions 2 for port A and 4 for port B.

    >> Yes, as mentioned in the TRM, the flash prefetch buffer is 2-deep for port A and 4-deep for port B.

    3.1) How come it is different since each port covers the same amount of data? (2Mb)

    >> Port B provides access to flash to all the non-CPU bus masters, hence deeper prefetch buffer.

    4) What is the replacement policy of Flash prefetch buffer lines? Round-robin?

    >> Again, not to be confused with the CPU cache - the flash prefetch buffer looks fetches the next sequential locations in flash memory on each access to the flash bank, that is, on each access that misses on the flash prefetch buffer.

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Intellectual 775 points

    4) Still, when the Flash fetches a new line on port A for example, does it put it in the line #1 or line #2? There is a replacement policy.

    Again, could you raise doc enhancement request for these infos to be added to TMS570LC TRM?

    Thanks.

  • 0 in reply to Etienne Alepins
    TI__Mastermind 49120 points

    Any miss in the prefetch buffer causes a read access to the flash bank. This information is forwarded directly to the CPU or other bus master, and the next sequential locations are prefetched into the port A/B buffers. So the entire prefetch buffer is replaced on a miss.

    Regards,

    Sunil