• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 521 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

CCS/TMS570LC4357: DMA Working Control Packets not updating in CCS

CCS/TMS570LC4357: Reading from DMA working control packet

Kevin Kriebs
Prodigy 40 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

I am having the same issue in reading the DMA Control Registers for Current DMA address using this LOC (dmaRAMREG->WPC[0].CDADDR).   This translates to accessing address 0xFFF80800. The default HalCOGen code for this memory region (0xFFF80000) is set the DEVICE_NONSHARABLE.  Changing the MPU configuration to cache write through did not make a difference.  Are there any other suggestions?

  • 0
    TI__Mastermind 49120 points

    Kevin,

    CPU write to a working control packet is not an allowed operation. These locations are read-only locations for the CPU so changing cache-write behavior will not make any difference.

    A working control packet is only updated if an active DMA channel loses arbitration to another DMA channel. Do you have multiple DMA channels active concurrently?

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    TI__Mastermind 49120 points

    Kevin,

    Please note that I have updated the title for the thread to refer to the topic being discussed.

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Prodigy 40 points

    Yes, there are 5 active DMA channels.  I am working with the two highest priority channels.  I am using the DMA channels with a HW trigger to move ADC1 and ADC2 data to SRAM.  So I should have an arbitration boundary between the ADC1 and ADC2 transfers.  If the control registers are updated at the arbitration boundary, shouldn't the register contain the address from the last completed DMA cycle?   

  • 0 in reply to Kevin Kriebs
    TI__Mastermind 49120 points

    The working control packet will be updated if a DMA channel is temporarily stopped to service the transfer request for another channel. It is not updated for a transfer that is completed. This typically happens for transfers of large number of blocks of data, where a channel gets arbitrated out at a frame boundary.