Why does the maximum ladder VIref (table 22-3) stop at 0xF (2.525v) Max when VDDA is >3v3? How can this be a useful VIRef level for highly restricted 3v3 comparator threshold when -Cn inputs are overly trigger happy? Is there a way to make VDDA input less sensitive to transients in light of less useful VIRef table values?
Typical use of internal analog comparators for PWM fault triggering is highly limited by it's design!