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Original question:

CPU reset triggered by STC test

TMS570LS3137: TMS570LS3137

Diana Rincon
Prodigy 40 points

Part Number: TMS570LS3137

I am implementing the LBIST selftest on the controller and when it resets, i read the CPURST bit on the (SYSESR) register and the value is 0x14. I would expect bit 5 to be set but it is not.

Anyone can give me a hint on this problem?

  • 0
    TI__Mastermind 21425 points

    Hello,

    LBIST has to set CPURST bit (SYSESR[5]). If bit 4 is set this means that Software reset is provoked. But bits SYSESR[2-0] should be read as 0 as stated in TRM and in your post bit 2 is 1 which is not normal. Can you confirm your observations and that you are reading the right register?

    Best regards,
    Miro

  • 0 in reply to Miro
    TI__Mastermind 21425 points

    Hello,

    I am going to close this thread assuming you have solved this issue. You can always reopen it with writing at the end. You can open new thread as well.

    Best regards,
    Miro