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TM4C123GH6PM: How to wake up TM4C123x MCU from hibernation mode when VDD is applied ?

Mehmet Kazakli
Prodigy 50 points
Part Number: TM4C123GH6PM
Hi everybody out there,
I have a question about wakes-up from hibernation mode.
"TM4C123x MCU will enters to hibernation mode when Vdd is removed while Vbat is applied."
I configurated my design as mentioned above, connected battery source to Vbat, and power source to VDD. So when VDD is removed, MCU will enter to hibernation mode. 
Now, I want to wake up TM4C123x MCU from hibernation mode when VDD is applied.So how should i connect WAKE pin ?

The datasheet says :
Should WAKE pin connected to VDD with 1M pull-up ressistor in order to understand VDD is applied and wake up the MCU?
What does "assertion of WAKE pin " means ?  Logic 1 or 0 will be asserted to wake up the MCU ? There is not clear information about it .
 
  • 0
    Prodigy 50 points

     

    Here is the WAKE pin function, no information about logic level meanings. 

  • 0 in reply to Mehmet Kazakli
    Guru 117855 points

    While the vendor is skilled at giving 'direct' answers - my group prefers a more, 'General (thus reusable) Problem Solving Method.'

    You may:

    • carefully measure the '/WAKE' pin for signal level:
      • during 'normal' (non-hibernate) operation
      • and again - during 'hibernate' mode  (i.e. after you have removed VDD - just as you noted.)
    • that 2nd measure (/Wake's signal level - during 'hibernate') will provide a solid clue:
      • you must 'toggle or flip' the logic-level upon /WAKE - to recover the MCU from 'hibernate'
      • the "/" fronting 'WAKE' signals that 'Logic Low' is the active level (i.e. 'wakes' the MCU)

    Again - you should confirm the 'correctness' of this 'General Solution' - yet you may 're-use' such methods repeatedly - as you move forward in your investigation & development...

    Sometimes it proves possible to employ a, 'spare MCU GPIO' to effect certain MCU Control.    In this case - as (predictable) GPIO behavior becomes 'suspect or unavailable' during 'hibernate' - it proves best for you to employ a bi-polar, NPN small-signal transistor - configured as, 'Open Collector.'    (the Collector of that transistor ties directly to the /WAKE pin; the Emitter ties to Ground; and the Base lead may (then) pass thru a series resistor (1KΩ should be fine) and connect to a spare GPIO or a 'Wake' switch.   A 'Logic High' - applied to that series resistor - will (then) drive the /WAKE pin to Ground.)

  • 0
    TI__Guru*** 135355 points

    Hello Mehmet,

    As cb1 commented already, the /WAKE signal is marked as a low true therefore 'assertion of /WAKE pin' means that you would need to set the pin to a logic 0.

    Note that the WAKE pin uses the Hibernation module's internal power supply as the logic '1' reference. So essentially whichever power source is powering the hibernation module will help determine the logic '1' state. Per specs for GPIO I would imagine that it follows the same logic as minimum voltage to be read as a '1' is (0.65 * VDD).