TMS570LS3137: Startup tests

Hello,

HCLK = 180MHZ, VCLK = 80 and STCCLK = 90MHZ MHz are given in Table 8-2 not as a restriction but because given Test times (the last column) are measured at these clocks. STCCLK can be divided by 1..8 using CLKDIV field in STCCLKDIV register. So, there is no restriction.

Thanks Miro.

Can you provide us the details on how timing values are calculated. Since, we want to use the HCLK/GCLK to lower frequency values than what is provided in the document.

Also, I was requesting on CCM test (chapter 9 of spnu499c.pdf). Will the tests support even with 10 MHz of GCLK/HCLK? Can we run CCM self tests without executing cpu self tests?

Sure Miro, but without executing cpu self test and with clock frequency set to 10 MHz, we are not perform ccm self tests. Can you recheck and confirm it?

Note: It is working with HCLK configured to 180MHz but not with 10 MHz.

Hello,

Would you clarify what not working means? Flag is not raised or test is not reaching the end.

Hello,

You need to make sure that you run CCM selftest when you are not connected to the debugger.

Test s not reaching the end and we tried with and without debugger and the result is same.

Hello Screenivasan,

How did you configure the PLL? and what is the OSCIN for the device?

When you configure the PLL, the internal clock (OSCIN/refclkdiv) should be between 1MHz and OSCIN Frequency. Please double check your settings. For getting a slower PLL clock (10MHz) with OSCIN=16MHz, a bigger REFCLKDIV MIGHT be used.

Hi Wang,

Can we configure VCLK2R and VCLKR fields with 0 value? The reason is that we want VCLK(2) to be same as HCLK frequency. Can you please check and confirm on this?

OSCI freq is 16 MHz.

PLL1 is configured 20 MHz and VCLK and VCLK2 is intented to configure 20MHz, but with that, we are not able to complete CCM self tests.

Hello Screenivasan,

The VCLK can be HCLK/1, HCK/2, … or HCLK/16. Can you execute your code in normal mode (not selftest)? Can you post your PLL1 configuration? What is the reference clock divider?

Hi Wang,

With PLL1=VLCK1=VCLK2=GCLK=HCLK=20MHz and by commenting CPU, CCM self tests, it was working fine. But, when we enable CPU or CCM self tests, we are seeing the issue (not coming out of cpu/ccm self tests). Do we have any restrictions on clock frequencies when configured low (as to 20 MHz)?

*pllctl1 = (Uint32)((0x20000000UL)
| (0x1FUL << 24UL)
| (5UL << 16UL)
| (0x0E00UL));

And as i mentioned, reference clock divider will be zero in order to keep HCLK=VCLK=VCLK2.

Any updates on this?

Hi Wang,

Any information needed further. Can you please share your updates on this?

Hi Wang/Miro,

Any updates on this? Can you please share your inputs on this?

Sreenivasan,

CCM self-tests do not complete if the CPU has ever entered debug mode (halted) for any reason since the last power-on-reset. If you want to check if the CCM self-tests are working correctly, you should create a pass/fail marker (I/O pin for example), program the part, disconnect debugger, and then assert power-on-reset. Once you release this reset, the code for the CCM self-tests will be executed and you can look for the pass/fail marker. Essentially, you cannot use the debugger to run these self-tests.

Regards,

Sunil

Hi Sunil,

As mentioned earlier (Sep 4, 2019 2:19 PM In reply to Miro:Test s not reaching the end and we tried with and without debugger and the result is same.),

we notice the same behaviour with or without debugger. The behaviour is, CCM self tests are not completed. Can you please are there any dependency with respect to clock frequencies? We see this behaviour with VCLK=VCLK2= HCLK set to 20 Mhz.