Hello,
We are using the TMS570LC4357 and we need more information about the SPI links
In operational on our configuration, only the CPU of TMS570 is Master on SPI 1 to 4 (i.e. slave mode is not used).
Thus, the module is configured to function as Master and clock is internally generated.
The CPU is interfaced to a PLD/FPGA.
What is the minimum timing to be respected between two SPI accesses ? We do not find any information in TMS570 documentation about this.
We would like to know what is the shortest time during which the TMS570 deactivate the “Chip Select” between 2 SPI access, so that we can test that our SPI slave is compliant with this time.
Best regards,
Christopher
