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TMS570LS3137-EP: Detailed documentation for Processor Modes / Operating Modes

Mark Fletcher
Intellectual 260 points
Part Number: TMS570LS3137-EP
Other Parts Discussed in Thread: HALCOGEN

Hi there,

This is a traceability request relating to a TMS570LS3137-EP with ARM R4F core.

Having failed to find references myself (I've searched many documents for hours now), can anybody please help source two pieces of information from a relevant (TMS/R4F) & official documentation source (TI or ARM)?

  1. the processor / operating mode following reset - from a HALCoGen project there's a code comment "after reset the CPU is in Supervisor mode".
  2. the "CPS" instruction and values - from unofficial documentation and HALCoGen 16=User, 17=FIQ, 18=IRQ, 19=Supervisor, 23=Abort, 27=Undefined, 31=System.

Thank you very much!

  • 0
    TI__Mastermind 49120 points

    Hi,

    The TRM for the Cortex R4F processor (ARM documentation number DDI0363) clearly states the CPU behavior on a reset. See https://developer.arm.com/docs/ddi0363/latest/programmers-model/exceptions/reset

    As for the "Change Processor State" instruction, this is described as part of the instruction set definition in the ARM v7R Architecture Reference Manual (ARM document number DDI0406). This document is only available for ARM licensees. There are other sources available as reference for the ARM/Thumb2 instruction sets. The CPS instruction is described in these. It is also referenced in the DDI0363 manual, just the instruction encoding is not shown.

    Regards, Sunil