Tool/software: Code Composer Studio
I have been developing a product that uses a bootloader. My bootloader was working and the application had been working before I was pulled off of this project for a number of months. In the meantime I received a new board spin. Now I find that my UART interrupts no longer work. I added gioHigh and gioLow level interrupts and tested a gio input and it does not interrupt either. I am using code composer to run my application.
Even though this once worked I am suspicious that relocating my application is the root cause. When I did a bootloader on an STM32F407 I had to make a call to copy the interrupt table before jumping to my main application. I don't see that step in the Hercules forum. That makes me nervous. My bootloader's interrupt table is located at address 0x00000000. For my application the vector interrupt table is at 0x00020000.
Am I missing something?
I'm attaching my linker cmd files for both the boot loader: bl_link.cmd and for my application: sys_link.cmd.
Here's my bootloader main():
void main(void)
{
int i=0;
bool bReload = FALSE;
/** - Initialize SCI Routines to receive Command and transmit data */
sciInit();
hetInit(); // initialization of all HET ports, for example, HART RST pin by N2HET1[9]
gioInit(); // initialize GPIO
// poll the UART for the signal character
bReload = CheckForDownLoadCommand();
if ( !bReload )
{
// STM32F407 copies the interrupt table here. does Hercules need to do the same?
g_ulTransferAddress = (uint32_t)APP_START_ADDRESS;
((void (*)(void))g_ulTransferAddress)();
}
//EnterBootLoader
ConfigureUartDevice();
//
// Branch to the update handler. Use can1
//
UpdaterUART();
}
bl_link.cmd:
--retain="*(.intvecs)"
MEMORY
{
VECTORS (X) : origin=0x00000000 length=0x00000020
FLASH_API (RX) : origin=0x00000020 length=0x000014E0
FLASH0 (RX) : origin=0x00001500 length=0x0001EB00 //LS04x and RM42 Flash size is 0x60000
FLASH1 (RX) : origin=0x00020000 length=0x0003CB00 //LS04x and RM42 Flash size is 0x60000
SRAM (RW) : origin=0x08002000 length=0x00006000 //LS04x and RM42 SRAM size is 0x8000
STACK (RW) : origin=0x08000000 length=0x00002000
}
SECTIONS
{
.flash1 : type=NOINIT{} > FLASH1
.intvecs : {} > VECTORS
flashAPI :
{
Fapi_UserDefinedFunctions.obj (.text)
bl_flash.obj (.text)
--library= F021_API_CortexR4_BE.lib < FlashStateMachine.IssueFsmCommand.obj
FlashStateMachine.SetActiveBank.obj
FlashStateMachine.InitializeFlashBanks.obj
FlashStateMachine.EnableMainSectors.obj
FlashStateMachine.IssueFsmCommand.obj
FlashStateMachine.ScaleFclk.obj
Init.obj
Utilities.CalculateEcc.obj
Utilities.WaitDelay.obj
Utilities.CalculateFletcher.obj
Read.MarginByByte.obj
Read.Common.obj
Read.FlushPipeline.obj
Read.WdService.obj
Async.WithAddress.obj
Program.obj > (.text)
} load = FLASH_API, run = SRAM, LOAD_START(api_load), RUN_START(api_run), SIZE(api_size)
.text > FLASH0
.const > FLASH0
.cinit > FLASH0
.pinit > FLASH0
.data > SRAM
.bss > SRAM
}
Application's .cmd file, sys_link.cmd:
/*----------------------------------------------------------------------------*/
/* sys_link_freeRTOS.cmd */
/* */
/*
* Copyright (C) 2009-2016 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/
/* Linker Settings */
--retain="*(.intvecs)"
/* USER CODE BEGIN (1) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/
/* Memory Map */
MEMORY
{
VECTORS (X) : origin=0x00020000 length=0x00000020
KERNEL (RX) : origin=0x00020020 length=0x00008000
FLASHCRC(RW) : origin=0x00028020 length=0x00000040
FLASH0 (RX) : origin=0x00001500 length=0x0001EB00 //LS04x and RM42 Flash size is 0x60000
FLASH1 (RX) : origin=0x00028060 length=0x00037FA0
STACKS (RW) : origin=0x08000000 length=0x00000800
KRAM (RW) : origin=0x08000800 length=0x00000800
RAM (RW) : origin=(0x08000800+0x00000800) length=(0x00007800 - 0x00000800)
/* USER CODE BEGIN (2) */
/* USER CODE END */
}
/* USER CODE BEGIN (3) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/
/* Section Configuration */
SECTIONS
{
.flash0 : type=NOINIT{} > FLASH0
.intvecs : {} > VECTORS
/* FreeRTOS Kernel in protected region of Flash */
.kernelTEXT : {} > KERNEL
.cinit : {} > KERNEL
.pinit : {} > KERNEL
/* Rest of code to user mode flash region */
.text : {} > FLASH1
.const : {} > FLASH1
/* FreeRTOS Kernel data in protected region of RAM */
.kernelBSS : {} > KRAM
.kernelHEAP : {} > RAM
.bss : {} > RAM
.data : {} > RAM
.sysmem : {} > RAM
FEE_TEXT_SECTION : {} > FLASH1
FEE_CONST_SECTION : {} > FLASH1
FEE_DATA_SECTION : {} > RAM
/* USER CODE BEGIN (4) */
.section_to_be_verified_code: { *(.text) } > FLASH1, palign=8, fill=0xffffffff, crc_table(link_crc_table_name, algorithm = TMS570_CRC64_ISO)
.section_to_be_verified_consts: { *(.const) } > FLASH1, palign=8, fill=0xffffffff, crc_table(link_crc_table_name, algorithm = TMS570_CRC64_ISO)
.TI.crctab: > FLASHCRC palign=8
/* USER CODE END */
}
/* USER CODE BEGIN (5) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/
/* Misc */
/* USER CODE BEGIN (6) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/
