TMS570LS3137: Mibspi master receive error

Please note that all chip selects and SOMI[x] ad SIMO[x] where x = 1...5 are configured as GPIO except SOMI[0] and SOMI[0] and CS[0] on both master and slave.

Increased the master C2T and T2 delay to 255, but still same issue is observed.

Hello Sreenivasam,

The thread mentioned in your post is question in loop-back mode (MibPSI5 to MibSPI5). You use MibSPI 1 as master, and MibSPI3 as the slave. The MibSPI1 or MibSPI3 should not be configured to loop-back mode.

The MibSPI3 (slave) receives the data correctly from MibSPI1 (master), but the MibSPI1 (master) doesn't receive the all the data transmitted by MibSPI3 (slave). Is my understanding correct?

Can you please tell us the configuration for both MibSPI1 and MibSPI3? It would be helpful if you post your code used for your test.

Hi Wang,

Yes, we are not looping internally, instead, MIBSPI5 and MIBSPI3 are connected externally. MIBSPI5 is master and MIBSPI3 is slave.

Slave is receiving data correctly, but not master.

Its halcogen generated code for driver configuration and below is the application code to use it.

mibspiSetData(mibspiREG3,0,tx_data2);
mibspiTransfer(mibspiREG3,0);

mibspiSetData(mibspiREG5,0,tx_data1);
mibspiTransfer(mibspiREG5,0);
test_delay();
while(!mibspiIsTransferComplete(mibspiREG3,0));
while(!mibspiIsTransferComplete(mibspiREG5,0));

mibspiGetData(mibspiREG5,0,rx_data1);
mibspiGetData(mibspiREG3,0,rx_data2);

Hello,

In MibSPI slave mode, only CS can trigger the transfer group. The fields like trigger source and trigger event are not taken into account by the sequencer.

Is MibSPI5 used as master in your code?

Yes Wang, its between MibSPI5 and MIBSPI3.

The code looks fine. The sequence is also fine.

Correct, but first word received in mibspi5 is wrong. Any reason for this.

Hello Sreenivasam,

If SPIENA is not used, there should be at least 6 VCLK cycles of delay between two transfer. Please set WDELAY to 6 or larger.

In slave mode, the PRST field should be cleared to 0. Please double check the PRST field of TGxCTRL register.