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TMS570LS3137: Flash ECC startup tests

sreenivasan m
Genius 3705 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hi Team,

Could see that from manual for single bit Flash ecc tests, we can use any range of values in mirrored region. So, we declared a variable in flash as below:

const Uint32 flash_parity = 0xA5A5A5A5UL;
volatile Uint32* const flash_addr = (Uint32 *)(0x20000000UL+(Uint8*)(&flash_parity));

With this address, flash ecc tests fails. Can we declare a variable and test like above for single bit and multi bit ecc for flash? Could see that from halcogen generated code, it uses 0x20000000 address which usually contains c_int entry address. 

Please confirm.

  • 0
    Genius 3705 points

    To be more speciifc, i was referring to checkFlashECC method in sys_selftest.c file. Here, it uses flashBadECC1 whose value is 0x20000000. Instead of this, we want to test with a variable declare in flash with known value and test this? Will it work , do we have any dependency?

  • 0 in reply to sreenivasan m
    Genius 3705 points

    A quick response is highly appreciated

  • 0 in reply to sreenivasan m
    Genius 3705 points

    Can someone comment on this please?

  • 0 in reply to sreenivasan m
    TI__Mastermind 21425 points

    Hello,
    You question has been addressed and will be answered ASAP.

  • 0 in reply to Miro
    TI__Guru**** 196436 points

    Hello Sreenivasan,

    Yes, you can use any location to test the flash ECC: 1-bit ECC error or 2-bit ECC error.

    For example, if you have a data (0x5A5A5A5A5A5A5A5A) that you want to intentionally flip a bit and this data is stored at address location 0x00010000. To flip bit 60 in your data, you need to write 0x6B (refer to the Syndrome Table) into the test register (DATA_INV_PAR). If you enter 0x6B into the test register while in diagnostic mode 7 then the CPU will think that bit60 is bad and try to correct it. 

    To generate ECC error, what you need is to read from the mirrored address of 0x00010000 which is 0x20010000.

    The sequence to do this test would be:

    1. Make sure the true DMA module is off.
    2. Put 0101b into PAR_OVR_KEY and 101b into DAT_INV_PAR fields (00005Axxh) of the FPAR_OVR register (0x7C).
    3. Put the desired value in DAT_INV_PAR field of FPAR_OVR register.
    4. Put 7 in DIAG_MODE, and 5 in DIAG_EN_KEY of FDIAGCTRL (0x6C).
    5. Do a slave access of the desired address. Note this is the mirrored address location
    6. Put 0 in DIAG_MODE or A in one of the key fields to turn off this test.
    7. Check error registers for ECC errors. (0x14, 0x1C, 0x20).
    8. Repeat as necessary to test out the ECC.
    9. Put 0 in DIAG_MODE and A in both of the key fields to completely disable this test at the end of the test.
    10. Write 5400h to FPAR_OVR(0x7C) to clear DAT_INV_PAR and put 2 into PAR_OVR_KEY.

  • 0 in reply to QJ Wang
    Genius 3705 points

    Thanks wang,.can you share sample code to test accordingly?

  • 0 in reply to sreenivasan m
    Genius 3705 points

    Hi Wang,

    Also, ESM group1 channel 7 is asserted when parity error is detected in N2HET1/N2HET2 module. But, how to differentiate the error between N2HET1 ad N2HET2? Could see that HETPAR will hold the offset value from start of the HETRAM. So, how can we differentiate the source of error (not by using HETPPR register)?

  • 0 in reply to sreenivasan m
    TI__Guru**** 196436 points

    Hello Sreenivasan,

    You can use the checkFlashECC() generated by HALCoGen. But read the content from 0x20000000 + flash location of flash_parity.

    Is &flash_parity in your code is a location in flash?

    Please post your NHET question to a separate post. Thanks

     

  • 0 in reply to QJ Wang
    Genius 3705 points

    Sure Wang, will post N2HET issue in another thread. 

    Yes &flash_parity is in location of address 0x9150. I tried with your suggestion as the address is 0x20009150 with which the test case fails sometimes.

    Just wanted to check is there anything to be done?

  • 0 in reply to sreenivasan m
    TI__Guru**** 196436 points

    Hello Sreenivasan,

    Did your test follow the sequence in my previous post? Mode 7 diagnostic will set ECC_ZERO_FLG, but won't set D_UNC_ERR nor D_COR_ERR.

    What does "fails sometimes" mean?

  • 0 in reply to QJ Wang
    Genius 3705 points

    Sorry for delay, yes it was working fine when tested on other target.