• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 29 subscribers
  • Views 588 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Atomicity of LDMmode and STMmode instructions

Tony Morrell
Genius 4130 points

Hi,

I suspect that the multiple register move instructions LDMmode and STMmode on the TMS570 (32-bit processor) are not atomic in themselves. I wish to make an uninterruptable 64-bit copy (so two registers) and was looking to use these functions.

Can somebody please confirm that in this case, the two register moves that would be required could be interrupted, and so I need to find an alternative solution.

Thanks, Tony.

  • 0
    TI__Intellectual 1030 points

    They are not atomic and the read multiple or write multiple accesses could be interrupted.  If the system can guarantee that only one master is accessing, then the multiple accesses should occur uninterrupted. (ie. no arbitration loss to another master). 

  • 0 in reply to S Tsuei
    Genius 4130 points

    Hi Stephanie,

    I may not be able to guarantee that my read/writes will not be interrupted. I think I will need to disable interrupts around the instructions using intrinsics _disable_IRQ() and _enable_IRQ().

    Thanks, Tony.

  • 0 in reply to Tony Morrell
    TI__Intellectual 1030 points

    One followup point - if the LDM/STM are being used to access 64-bit aligned data in TCM RAM, the data (2x32 -bit registers) transfer will occur in a single cycle. (Cortex-R4 has 2x 64-bit interfaces to the RAM, and it will group two processor registers together to form a single 64-bit access.) This is specific to the TCM interface and it doesn't apply if  peripherals are being accessed.