CCS/TMS570LS3137: checkClockMonitor() in sys_selftest.c from HALCoGen - code freezes waiting for oscillator to fail.

Thomas Pikett

Intellectual 580 points

Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

/* Wait till oscillator fail flag is set */

/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */

while((systemREG1->GBLSTAT & 0x1U) == 0U)

{

} /* Wait */

I am using a 10Mhz oscillator and a PLL1. When checkClockMonitor is called the clocks have been set up.

HALCoGen version is 04.07.00. CCS is 8.2.0.00007.

The sys registers at this point are:

ffffff00

========

0x00000000

0x00000001

0x00000000

Sys_SysPc9

0x00000001 0x00000020 0x00000000 0x00000000

Sys_CsDis

0x0000008C

Sys_CdDis

0x00000400

Sys_GhvSrc

0x01010001

Sys_VclkASrc

0x00000909

Sys_RclkSrc

0x01090109

Sys_CsVStat

0x000000FB

Sys_MstGlbCtrl

0x00000105

0x00000005

0x00000000

Sys_PllCtl1

0x20049F00

Sys_PllCtl2

0x3FC0723D

0x00000000

Sys_DieIdl

0x0F01E01E

Sys_DieIdh

0x08036F54 0x00000000

Sys_LpoMonCtl

0x01001310

Sys_ClkTest

0x000A0000

0x00002205

0x00000005 0x00000000 0x00000000

0x0005FFFF 0xDEFA0005

0x00000000

0x00050000

0x0000000A

0x00000000

0x01010100

0x00000007 0x00000000

0x0000000A

0x00004000

0x00000008

0x00000000

Sys_GlbStat

0x00000000

Sys_DevId

0x802AAD1D

0x00000000

0x00000000 0x00000000

The HALCogen set up is:1768.V1 clockmonitor.docx

over 5 years ago

0 QJ Wang over 5 years ago

TI__Guru**** 196286 points

Hello,

To do this test, the GCLK/HCLK/VCLK's clock source should be changed to HF LPO, and the clock range detection should be enabled:

1. GHVSRC should be 0x05050005; but this register in your test is 0x01010001

2. Bit 0 of CSDISSET should be set; but the 1st in your test is cleared: 0x0000008C

3. CLKTEST = 0x03xxxxxx; but the clock range detection is not enabled in your test

0 Thomas Pikett over 5 years ago in reply to QJ Wang

Intellectual 580 points

Hi,

For reasons that escape me the register settings I sent were incorrect. Sorry about that.

On further examination they do largely match the settings you have given. CsDis is 8D rather than CD.

CsVStat is B8 rather than 38.

Could it be because I am using PLL1 to do the important things and it is derived from the oscillator the oscillator cannot be disabled?

Does PLL1 have to be disabled as well?

Regards,

Tom

0 QJ Wang over 5 years ago in reply to Thomas Pikett

TI__Guru**** 196286 points

Hello Tom,

As I mentioned din my previous post, the OSC needs to be disabled to cause the oscillator fail. You don't need to disable PLL.

The bit 0 of CSDISSET is for oscillator.

0 QJ Wang over 5 years ago in reply to QJ Wang

TI__Guru**** 196286 points

Hello Tom,

1. The low power oscillator (LPO) produces 2 frequencies: HF LPO, and LF LPO

2. The HF LPO is used to monitor the oscillator input frequency

3. If the oscillator frequency fails, the clock detects will supply HF LPO as clock source. Channel 11 of ESM group is set.

4. You need to enable the clock detect circuitry (CLKDETECT register)

0 Thomas Pikett over 5 years ago in reply to QJ Wang

Intellectual 580 points

Thanks for that. I've been diverted onto another project so I think it is ok to close this. I will open another when I get back - if latest info does not cure it. Thanks.

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CCS/TMS570LS3137: checkClockMonitor() in sys_selftest.c from HALCoGen - code freezes waiting for oscillator to fail.