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TM4C1294NCPDT: Timing of chip select on the EPI interface for TM4C1294?

Julio Apps
Expert 3665 points
Part Number: TM4C1294NCPDT

Hello Team,

Would you be able to help me understand the timing of the chip select on the EPI interface of the TM4C1294NCPDT when configured for host bus 16 using a multiplexed address and data bus?

 

I don’t see any Read timings diagrams but there are two Write timing diagrams shown in the manual (datasheet).  Figure 11-14 and figure 11-15.  11-15 looks closer to what I need with the CS asserting and valid when the address strobe is active.

 

But figure 11-14 show the chip select going active much later. Why is it different and how do I control it?  What does the read do?

  • 0
    TI__Guru*** 135355 points

    Hello Julio,

    I think the detailed description in the datasheet helps explain a lot to accompany these images, but there is a lot of information there so I will try and highlight the key passages.

    Whether or not the Chip Select is pulsed low at different times is going to depend on the configuration of the CSn. If there is only one chip select, then you will get the behavior on Figure 11-14. This is because the CSn indicates when the address and data phases of a read or write access are occurring.

    This passage from Section 11.4.3.1 Control Pins may help with deciding how to setup the EPI:

    "The ALE can be changed to an active-low chip select signal, CSn, through the EPIHBnCFGn register. The ALE is best used for Host-Bus muxed mode in which EPI address and data pins are shared. All Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an external latch to capture the address then hold it until the data phase. The polarity of the ALE can be active High or Low by clearing or setting the ALEHIGH bit in the EPI Host-Bus n Configuration (EPIHBnCFGn) register. CSn is best used for Host-Bus unmuxed mode in which EPI address and data pins are separate. The CSn indicates when the address and data phases of a read or write access are occurring. Both the ALE and the CSn modes can be enhanced to access four external devices using settings in the EPIHBnCFGn register."

    It sounds to me like you may want to leverage the ALE signal more on the slave device if that is possible. Something to look into as far as the slave device capabilities.

    If that is not possible, then for the CS specifically, perhaps you can leverage the behavior that occurs when configuring for multiple CSn lines: "When using ALE with dual CSn configuration (CSCFGEXT bit is 0 and the CSCFG field is 0x3 in the EPIHBnCFG2 register) or quad chip select (CSCFGEXT bit is 1 and CSCSFG is 0x2), the appropriate CSn signal is asserted at the same time as ALE, as shown in Figure 11-15."

    Regards the read portion: "Figure 11-14 on page 846 shows a write cycle with the address and data signals multiplexed (MODE field is 0x0 in the EPIHBnCFG register). A read cycle would look similar, with the RDn strobe being asserted along with CSn and data being latched on the rising edge of RDn."

  • 0 in reply to Ralph Jacobi
    TI__Expert 3665 points

    Ralph,

    You are  indeed the Guru! Thank you so much for the clarification.