Other Parts Discussed in Thread: HALCOGEN
Hello,
I am working on the Hercules TMS570LC43x Development Kit to mock-up software for a future board. I have the following requirements about the clocks configuration:
- GCLK at 240 MHz.
- HCLK at 120 MHz.
- VCLK at 40 MHz.
I also enable the SCI1 as a serial debug output with the following parameters:
- Baudrate at 115 200.
- 1 stop bit.
- 8 bits length.
HALCoGen (04.07.01) configures automatically the Prescale register with value 21 due to the 40 MHz VCLK input clock. The value is consistent with the technical reference manual.
After building and executing the code I observe invalid characters on my terminal which mean that the output frequency of serial line is probably not correct. A quick measurement with oscilloscope shows that frequency is stable and nearly around 170 MHz. It was a surprise because I used SCI1 with several clock configurations before and I never observed any problem.
I modified the reference configuration to a modified one. I just change the VCLK1 divider to modify the frequency from 40 MHz to 60 MHz. As a consequence HALCoGen updated the Prescale register of the SCI1 from 21 to 32 to fulfill the requirements and it works perfectly.
I don't understand why the original configuration lead to a bad serial output frequency. All constraints about clocks and SCI module seem to be fulfill.
I put the 2 projects as attached files to help you to investigate.
Regards,
