TMS570LC4357: Deliberate ECC Errors for FMC ECC Checking

Hello,

You can take a look at this thread where QJ explains how Deliberate single bit and double bit errors can be used:

The processor takes the data abort if data should be read from or written to a protected or faulty memory location.
This could be because of:
•  The memory location is not implemented
•  The memory location is read or write only in privileged mode (when processor is in User mode )
•  The memory location is read or write protected by the MPU
•  If an error is detected in the data by the ECC checking logic

The above list may not be complete. For more details about the data abort, see the ARM Cortex-R4 and Cortex-R4F Technical Reference Manual
(ARM DDI 0363C).

Hello,

I already tried to change MPU access right and it did not change anything.

I did not found another solution in the related topic.

What do you mean by the region is not implemented ?

Thanks,

Regards

Hi any update about this issue ? Is there some register to initialize first to be able to read this area ?

Thanks

Little update about the issue.

I forgot the PMCR bit X and now it generates 2 bit ECC errors by raising flag 2.3 from the ESM.

Yet when reading TMS570LC4347 datasheet 6.20 Reset / Abort / Error Sources

Table 6-46. Reset/Abort/Error Sources : Flag supposed to be raised is 2.19.

And also concerning SEU errors flag 1.6 is supposed to be raised but no flags is raised, not even 1.26. I also tried to set channel 6 as HIGH Level Interrupt but it did not change anything.

Also no status flags is raised in Flash Wrapper registers.

Is there anything I m missing ?

Thanks