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RM48L952: RM45L952

Part Number: RM48L952


How we need to map the address/memory for 8-bit/16-bit Flash/SRAM using EMIF I/F of RM48L952 Microcontroller ? and what is the reason behind these type of mapping ?

  • Hello,

    Section 17.2.6.1 in device TRM describes interfacing to 8/16 bit Asynchronous Memory.

    Of special note is the connection between the EMIF and the external device's address bus. The EMIF address pin EMIF_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when interfacing to a 16-bit or 8-bit asynchronous device, the EMIF_BA[1] and EMIF_BA[0] pins provide the least-significant bits of the halfword or byte address, respectively. Additionally, when the EMIF interfaces to a 16-bit asynchronous device, the EMIF_BA[0] pin can serve as the upper address line EMIF_A[22].

  • What is the reason behind these kind of bit shift mapping ? not only in this RM48L952 microcontroller, in other manufacturers also some of BUS mapping will be present like this. 

  • Hello,

    It is by design. I am not aware with the silicon design decisions.

    By design The EMIF address pin EMIF_A[0] always provides the least significant bit of a 32-bit word address. Therefore additional signals for 8bit and 16bit addressing are required.