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TMS570LC4357: prefetchEntry Exception Error - Input welcomed

Part Number: TMS570LC4357

Team,

Trying to assist our customer in determining why they are getting the prefetchEntry exception as follows:

(First, realize the purpose of executing the F021 library from SRAM is to allow flashing sectors in Bank 0;  they will prevent erasing/writing to flash memory addresses in sectors where the boot-loader resides.  Otherwise the usable (by application) flash memory is cut in half.)

The following line is where the porefetchEntry interrupt occurs; arguments:

                Fapi_EraseSector    = 0x0006

current_sector_start_address = 0x00100000 (sector 12, Bank 0)

 

        fapi_status = Fapi_issueAsyncCommandWithAddress(Fapi_EraseSector,

                                                        (uint32_t *)current_sector_start_address);

 

Screenshot after pausing execution when development board seems to lock up stepping over issueAsyncCommandWithAddress();

  

The flash API (F021 library) has been moved to SRAM; more specifically Fapi_issueAsyncCommandWithAddress() is at 0x08001F94.

Calling Fapi_issueAsyncCommandWithAddress() with the following arguments works fine:

                Fapi_EraseSector    = 0x0006

current_sector_start_address = 0x00200000 (sector 0, Bank 1)

Any input welcomed.

TY,

CY

  • Chris,

    Was it always successful in erasing bank 0 but not bank 1?

    When you see the issue, can you please check CP15 fault status register? Can you provide some screenshot of that?

    CP15_DATA_FAULT_STATUS
    CP15_INSTRCUNCTION_FAULT_STATUS
    CP15_DATA_FAULT_ADDRESS
    CP15_INSTRUCTION_FAULT_ADDRESS

    Also what is the LR register which will show the return address?

    best regards,

    David Zhou

  • Chris,

    Just to follow up on this E2E thread, do you have any update? The CP15 fault registers will help in finding out what has caused the exception.

    best regards,

    David Zhou

  • Hi David,

    Attempting to write to address 0x001C0000 two bytes of data (0x55, 0xAA).

     fapi_status = Fapi_initializeFlashBanks( SYS_CLK_FREQ );

    ð  SYS_CLK_FREQ = 150

    ð  returns Fapi_Status_Success

     

    fapi_status = Fapi_setActiveFlashBank( (Fapi_FlashBankType)current_bank );

    ð  current_bank = 0, returns Fapi_Status_Success

     

    fapi_status = Fapi_enableMainBankSectors( 0xFFFF );

    ð  returns Fapi_Status_Success

     

    fapi_status = Fapi_issueAsyncCommandWithAddress(Fapi_EraseSector, (uint32_t *)current_sector_start_address);

    ð  Fapi_EraseSector = 6, current_sector_start_address = 0x001C0000, does not return; jumps to “prefetchEntry” interrupt vector

     

    Here’s the information you requested; note: the LR register is holding the address of the prefetchEntry ISR.

    Also, please verify Fapi_issueAsyncCommandWithAddress() can be used when it resides in SRAM.

     

     

    Cp15

         CP15_ID_CODE                    0x411FC152 MIDR [Core]    

         CP15_CACHE_TYPE                 0x8003C003 CTR [Core]

         CP15_TCM_TYPE                   0x00010001 TCMTR [Core]   

         CP15_MPU_TYPE                   0x00001000 MPUIR [Core]   

         CP15_MULTIPROCESSOR_ID          0xC0000000 MPIDR [Core]   

         CP15_PROCESSOR_FEATURE_0        0x00000131 PFR0 [Core]    

         CP15_PROCESSOR_FEATURE_1        0x00000001 PFR1 [Core]    

         CP15_DEBUG_FEATURE_0            0x00010400 DFR0 [Core]    

         CP15_AUXILIARY_FEATURE_0        0x00000000 ID_AFR0 [Core] 

         CP15_MEMORY_MODEL_FEATURE_0      0x00210030 ID_MMFR0 [Core]

         CP15_MEMORY_MODEL_FEATURE_1      0x00000000 ID_MMFR1 [Core]

         CP15_MEMORY_MODEL_FEATURE_2      0x01200000 ID_MMFR2 [Core]

         CP15_MEMORY_MODEL_FEATURE_3      0x00000211 ID_MMFR3 [Core]

         CP15_INSTRUCTION_SET_ATTRIBUTE_0 0x02101111 ID_ISAR0 [Core]

         CP15_INSTRUCTION_SET_ATTRIBUTE_1 0x13112111 ID_ISAR1 [Core]

         CP15_INSTRUCTION_SET_ATTRIBUTE_2 0x21232141 ID_ISAR2 [Core]

         CP15_INSTRUCTION_SET_ATTRIBUTE_3 0x01112131 ID_ISAR3 [Core]

         CP15_INSTRUCTION_SET_ATTRIBUTE_4 0x00010142 ID_ISAR4 [Core]

         CP15_INSTRUCTION_SET_ATTRIBUTE_5 0x00000000 ID_ISAR5 [Core]

         CP15_CURRENT_CACHE_SIZE_ID      0xF01FE019 CCSIDR [Core]  

         CP15_CURRENT_CACHE_LEVEL_ID      0x09200003 CLIDR [Core]   

         CP15_CACHE_SIZE_SELECTION       0x00000000 CSSR [Core]    

         CP15_SYSTEM_CONTROL              0x8BE7187D SCTLR [Core]   

         CP15_AUXILIARY_CONTROL          0x00000000 ACTLR [Core]   

         CP15_COPROCESSOR_ACCESS         0xC0F00000 CPACR [Core]   

         CP15_DATA_FAULT_STATUS          0x00000000 DFSR [Core]    

         CP15_INSTRUCTION_FAULT_STATUS    0x00001008 IFSR [Core]    

         CP15_AUX_DATA_FAULT_STATUS      0x00000000 ADFSR [Core]   

         CP15_AUX_INSTRUCTION_FAULT_STATUS     0x00000000 AIFSR [Core]   

         CP15_DATA_FAULT_ADDRESS         0x00000000 DFAR [Core]    

         CP15_INSTRUCTION_FAULT_ADDRESS   0x0000000C IFAR [Core]    

         CP15_MPU_REGION_BASE_ADDRESS     0xFFF80000 Core

         CP15_MPU_REGION_SIZE_ENABLE      0x00000025 Core

         CP15_MPU_REGION_ACCESS          0x00001210 Core

         CP15_MPU_REGION_NUMBER          0x0000000F Core

         CP15_TCM_ATCM_REGION             0x00000000 ATCMRR [Core]  

         CP15_TCM_TCM_SELECTION          0x00000000 TCMSR [Core]   

         CP15_PERFORMANCE_MONITOR_CONTROL 0x41151810 PMCR [Core]    

         CP15_COUNT_ENABLE_SET            0x00000000 PMCNTENSET [Core]    

         CP15_COUNT_ENABLE_CLEAR         0x00000000 PMCNTENCLR [Core]    

         CP15_OVERFLOW_FLAG_STATUS       0x00000000 PMOVSR [Core]  

         CP15_SOFTWARE_INCREMENT         0x00000000 PMSWINC [Core] 

         CP15_COUNTER_SELECTION          0x00000000 PMSELR [Core]  

         CP15_CYCLE_COUNT                 0x00000000 PMCCNTR [Core] 

         CP15_EVENT_SELECTION             0x00000000 PMXEVTYPER [Core]    

         CP15_PERFORMANCE_MONITOR_COUNT   0x00000000 PMXEVCNTR [Core]

         CP15_USER_ENABLE                 0x00000000 PMUSERENR [Core]

         CP15_INTERRUPT_ENABLE_SET       0x00000000 PMINTENSET [Core]    

         CP15_INTERRUPT_ENABLE_CLEAR      0x00000000 PMINTENCLR [Core]    

         CP15_SLAVE_PORT_CONTROL         0x00000000 AXI Slave Port Control [Core]    

         CP15_FCSE_PID                   0x00000000 FCSEPID [Core] 

         CP15_CONTEXT_ID                 0x00000000 CONTEXTIDR [Core]    

         CP15_USER_READ_WRITE_THREAD_PROCESS_ID      0x00000000 Core

         CP15_USER_READ_ONLY_THREAD_PROCESS_ID      0x00000000 Core

         CP15_PRIVILEDGED_ONLY_THREAD_PROCESS_ID     0x00000000 Core

         CP15_SECONDARY_AUXILIARY_CONTROL 0x00400000 Core

         CP15_NVAL_IRQ_ENABLE_SET        0x00000000 Validation IRQ Enable Set Register [Core]

         CP15_NVAL_FIQ_ENABLE_SET        0x00000000 Validation FIQ Enable Set Register [Core]

         CP15_NVAL_RESET_ENABLE_SET      0x00000000 Validation Reset Enable Set Register [Core]

         CP15_NVAL_DEBUG_REQUEST_ENABLE_SET    0x00000000 Validation Debug Request Enable Set Register [Core]

         CP15_NVAL_IRQ_ENABLE_CLEAR      0x00000000 Validation IRQ Enable Clear Register [Core]

         CP15_NVAL_FIQ_ENABLE_CLEAR      0x00000000 Validation FIQ Enable Clear Register [Core]

         CP15_NVAL_RESET_ENABLE_CLEAR     0x00000000 Validation Reset Enable Clear Register [Core]

         CP15_NVAL_DEBUG_REQUEST_ENABLE_CLEAR  0x00000000 Validation Debug Enable Clear Register [Core]

         CP15_BUILD_OPTIONS_1             0x00000000 Core

         CP15_BUILD_OPTIONS_2             0x403FF9DD Core

         CP15_CORRECTABLE_FAULT_LOCATION  0x00000000 Core   

     

    Core Registers  Core Registers 

         PC   0x0000000C Program Counter [Core]    

         SP   0x08001400 General Purpose Register 13 [Core]   

         LR   0x00000010 General Purpose Register 14 [Core]   

         CPSR 0x600003D7 Stores the status of interrupt enables and critical processor status signals [Core] 

         R0   0x00000000 General Purpose Register 0 [Core]    

         R1   0x00000006 General Purpose Register 1 [Core]    

         R2   0xFFF87288 General Purpose Register 2 [Core]    

         R3   0x00002194 General Purpose Register 3 [Core]    

         R4   0x00000005 General Purpose Register 4 [Core]    

         R5   0xFFFFFF68 General Purpose Register 5 [Core]    

         R6   0x00000000 General Purpose Register 6 [Core]    

         R7   0x00000000 General Purpose Register 7 [Core]    

         R8   0x00000000 General Purpose Register 8 [Core]    

         R9   0x00000000 General Purpose Register 9 [Core]    

         R10  0x00000000 General Purpose Register 10 [Core]   

         R11  0xFFFFFF60 General Purpose Register 11 [Core]   

         R12  0x08001F25 General Purpose Register 12 [Core]   

         R13  0x08001400 General Purpose Register 13 [Core]   

         R14  0x00000010 General Purpose Register 14 [Core]           

     Thanks,
    Chris

  • Chris,

    From the CP15 IFSR register we know it is a synchronous external abort. IFAR is supposed to have the address which caused the fault but its value is 0x0c, it seems to have pointed to a vector table address.

    Is it possible that you can create a test case which demos this issue? I don't need all the code but the minimum that demos the issue is fine.

    best regards,

    David Zhou

  • David,

    I am sending you an example workspace separately.

    Thank you very much.

    Regards,

    Chris

  • Chris,

    The problem I found in your projects are as follows:

    1.The function which calls Flash API function can’t be in the same bank, it will have to be in another bank or RAM. I have moved it to RAM since that was the intention ==> the .cmd file has been modified;

    2.Now RAM need to be executable ==> the .cmd file has been modified;

    3.Const section not been copied. ==> the .cmd file has been modified and also the main function modified to copy const section from flash to RAM as well.

    With above changes, the project works fine now.


    best regards,


    David Zhou

     

  • Hello David,

    I believe we should be able to close this out now, pending final confirmation.

    But I thank you for your help regardless.

    Best regards,
    Chris