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TMS570LS3137: MibSPI mode operation one slave SPI device with 2 data formats (word length different)

Chuck Wong
Genius 3950 points
Part Number: TMS570LS3137

Hello there,

We've to interface the MCU MibSPI module in master mode with a slave SPI device having an instructions-set of 8-bit, but the device register size are 16-bit, so every time when a read/write command is issued, we have to push 16 SPICLK through to complete the operation.

In order to save the number of BUFID locations to exchange data with the slave SPI device, I'm wondering whether it is possible to, while the nCS is asserted ...

Shift the write command using SPIFMT0 with data length of 8 (SOMI = high impedance)
Shift 16 SPICLK to write data word using SPIFMT1 with data length of 16 (SOMI = high impedance)
Shift the read command using SPIFMT0 (SOMI = high impedance)
Shift 16 SPICLK to read data word using SPIFMT1 (MibSPI RXRAM BUFID[x] should contain the 16-bit data word RX from the device)

Questions:

  1. Does the MCU accept data format switching on the fly like this?
  2. May I assume the outcome of the last operation (i.e. 16-bit data word stored in TXRAM BUFID[x])?

Many thanks.

  • 0
    Genius 3950 points

    Hi again,

    I've another question in relation with the Transfer Group TG and TXRAM CS_HOLD and BUFID_LOCK settings.

    We need to write a table of 256x16-bit words to the SPI, and since the TXRAM is only 128x16-bit large, I would like to use the following procedure:

    1. Initiate the write opcode with TG0 and set CS_HOLD & BUFID_LOCK at the last BUFID[x] and wait for TG completion
    2. Reprogram TG0 with the first half with 128x16-bit words, and set CS_HOLD & BUFID_LOCK at BUFID[127], then trig TG0 and wait for TG completion
    3. Reprogram TG0 with the second half with 128x16-bit words, and clear CS_HOLD & BUFID_LOCK at BUFID[127], then trig TG0 and wait for TG completion

    Will this works to write more than 128x16-bit words to the SPI device?

    Thanks.

  • 0 in reply to Chuck Wong
    Genius 3950 points

    Please anyone can shed some light on my questions?

    Thanks.

  • 0 in reply to Chuck Wong
    TI__Mastermind 21425 points

    Hello,

    Sorry for the delay. You question is addressed to our expert and will be answered ASAP.

  • 0 in reply to Miro
    Genius 3950 points

    Hello,

    As we're finalizing the design for the MibSPI TXRAM and proceed to the design review, it would really be appreciated that our approach and understanding could be confirmed quickly.

    Thank you very much.

  • 0 in reply to Chuck Wong
    TI__Guru**** 197306 points

    Hello Chuck,

    Can you tell you like to change the charlen on the fly?

    My answer is yes, you can change the charlen at any time, but you must make sure that master and slave are configured to have the same Data Word Length. You need to define a communication protocol to tell the slave when you change the charlen. 

    1. At Charlen = len1 (8 or 16)

    2. Master TX the command of changing charlen

    3. Master TX the new charlen

    4. Master TX a dummy message to make sure that the Slave has make the change

    5. Master change the charlen to len2

    6. Master TX TX data with new configuration (len2)

    BUFIDx is only used for DMA transfer. You can use 127 buffers or any number of buffers in TXRAM to transfer data from your 256x16 table. 

  • 0 in reply to QJ Wang
    Genius 3950 points

    Hi QJ,

    Thank you for the reply.

    In fact it should be much simpler, there will be no handshake for the charlen change, since following a 8-bit read or 8-bit write command, the slave expects always multiple of 16 SPI clocks (internal register size if 16 bits).

    At the slave standpoint, I believe that either it receives 2x8-bit or 1x16-bit sent by the MibSPI master, it doesn't make any difference, it will just receive 16 SPI clock without interruption.

    The MCU MibSPI will not create any error for doing so. Do you agree with my assessment?

    Thanks.

  • 0 in reply to Chuck Wong
    Genius 3950 points

    Chuck Wong said:

    Hi again,

    I've another question in relation with the Transfer Group TG and TXRAM CS_HOLD and BUFID_LOCK settings.

    We need to write a table of 256x16-bit words to the SPI, and since the TXRAM is only 128x16-bit large, I would like to use the following procedure:

    1. Initiate the write opcode with TG0 and set CS_HOLD & BUFID_LOCK at the last BUFID[x] and wait for TG completion
    2. Reprogram TG0 with the first half with 128x16-bit words, and set CS_HOLD & BUFID_LOCK at BUFID[127], then trig TG0 and wait for TG completion
    3. Reprogram TG0 with the second half with 128x16-bit words, and clear CS_HOLD & BUFID_LOCK at BUFID[127], then trig TG0 and wait for TG completion

    Will this works to write more than 128x16-bit words to the SPI device?

    Thanks.

    Please also would like an answer to this question.

    Thank you for following up.

  • 0 in reply to Chuck Wong
    TI__Guru**** 197306 points

    Hello Chuck,

    Your method works.