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TMS570LS3137: How to enable ECC for PFlash and SRAM using C language?

Lakshmikanth R S
Intellectual 790 points
Part Number: TMS570LS3137

According to the TI safety manual, I understood

1. SRAM ECC can be enabled by setting B1TCMPCEN and B0TCMPCEN bits of the System control coprocessor’s Auxiliary control register, c1 

2. PFlash ECC can be enabled by setting the ATCMPCEN bit of the System control coprocessor’s Auxiliary control register, c1.

I found some assembly code snippets for accessing Auxiliary control register, c1.

Since we are using C-language in our project, so kindly share the details on how to use C-language to access Auxiliary control register, c1?

  • 0
    TI__Mastermind 49120 points

    Hello,

    There are several other cases where an assembly routine is used. An assembly routine is typically used when accessing / configuring coprocessor registers in the Cortex-R4/R5 CPU. The compiler does not generate these special instructions for accessing coprocessor registers.

    As such the C routines can still call these functions using their "labels". For example, the CPU's event bus signals are exported from the CPU by enabling it in a coprocessor. This is done by calling the _coreEnableEventBusExport_() function.

    Do you have an issue with having .asm files in your project? If so, you can create .c files and put in "asm" functions like this:

    asm(" nop");

    Above example is for executing a "NOP" assembly instruction. This line could be part of a .c file. The compiler does not try and optimize this line.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 790 points

    Hi Sunil,

    I am facing CPU abort issue after enabling flash and SRAM ECC.

    I have enabled Flash/SRAM ECC in auxiliary control system register and enabled export of the events to the event bus in  c9, Performance Monitor Control Register. I have verified the values of these CPU registers in CCS.

    I have a function in my code in which I am copying the data from Flash to RAM. My program execution aborts at this function when Flash and SRAM ECC is enabled.

    Please note that I am programming the code in the target with "Auto ECC generation' enabled in CCS.

    I am confused why CPU aborts though I have enabled "Auto ECC generation". Please let me if I am doing something wrong here.

  • 0 in reply to Lakshmikanth R S
    TI__Mastermind 49120 points

    Please use the CPU's abort status and abort address registers to identify the cause of abort. Are you getting a prefetch abort (on instruction fetches) or a data abort (on data accesses)?