Hi Team,
I could see from the HET micro instructions that it can access Data portion of the HET micro instructions. Can there be any way that we can access core memory (TCRAM) from HET micro code instructions?
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Hi Team,
I could see from the HET micro instructions that it can access Data portion of the HET micro instructions. Can there be any way that we can access core memory (TCRAM) from HET micro code instructions?
HET cannot directly access any memory other than the HET memory itself. You can write instructions that modify other instructions' control/data fields.
You can, however, generate DMA / HTU trigger events from a HET program that can transfer values to / from the TCRAM. These trigger events are synchronized to the HET program execution. Both the DMA and HTU accesses have separate MPUs that must be programmed to ensure that they don't accidentally overwrite TCRAM locations used by other bus masters, e.g. CPU stack.
Regards, Sunil
You can refer to this application note: http://www.ti.com/lit/an/spna130a/spna130a.pdf
The code example is written for a different MCU, but you can follow the sequence and implement it for TMS570LS3137 as well.
You can also refer to this post in case you run into a similar issue: https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/824569
Regards, Sunil
Thanks Sunil, I tried the similar steps on TMS570LS3137 controller, but could not see the data into bufferA nor bufferB.
Note, we are not configuring MPU, so i believe it doesn't impact. Can you please test on and confirm?
Also, if we want to control the execution of HET from core say allow to execute het module for few lrp periods only and then wait for signal from core to execute further.
Sreevivasan,
I don't have another example for the usage of HTU other than the one I provided already. You do need to configure the MPU to define the memory region to where HTU is writing to be "shareable" between the CPU and the HTU.
As for your second question, the HET is built to be significantly independent of the CPU. That said, the CPU does get to turn the HET ON and can also turn it OFF. Turning OFF the HET makes it stop at the loop boundary. However, you do lose all the status flags. Counting HET time base periods (LRP) in the CPU will be difficult.
A suggestion: you can architect a scheme where the HET program looks at a HET instruction's data field to be a certain value before continuing with the rest of the HET program in a loop. Then the application can control execution of the HET loop by writing different values to the data field. This way the start / stop of the HET remains synchronized to the LRP, under the application's control, and will maintain the status of all flags.
Regards, Sunil
Hi Sunil,
Tried with mpu enabled, but still it (single buffer mode) is not working. Also, enabled IRQ in HET instructions and corresponding Interrupt flags are set in HET and VIM, but interrupt handler is not getting executive.
Interrupt is configured for 4th instruction (0,1,2,3) and on pin 0 mapped to Int level 0.
Please find the snapshot for reference.
Can you please check and let me know if we need to do anything further on these?

The screenshot shows HET generating a level 1 interrupt mapped to channel 24 of VIM. The flag is also set in the VIM. This interrupt channel needs to be enabled within the VIM for the interrupt request to be sent to the CPU. You have the channel 24 masked out in the screen shot. Please set bit 24 of ReqMaskSet0 for the interrupt request to be forwarded to the CPU.
Some things to check: