Hi,
I have a question regarding the hardware status bit check in the HALCoGen-generated function spiReceiveData in spi.{h,c}.
After writing to spi->DAT1, which sets data format, nCS, nCS hold, delay and enables SPI clk, the function enters a while loop, which looks like the following:
while((spi->FLG & 0x00000100U) != 0x00000100U)
{
} /* Wait */
Which is quite simply a check on bit nr. 9 of the SPI Flag register. But Table 28-13, page 1542, of SPNU563A (March 2018) states that this bit is the TXINTFLG (1 if transmit buffer is empty, which is what this loop is waiting for).
Wouldn't it be more appropriate to wait on bit nr. 8 RXINTFLG to become 1 as this indicates a newly received data ready to be read?
Regards,
Christophe
