I want to capture and raise ESM error for the ECC errors in OTP memory. In the datasheet, I could not find ESM channel assigned for OTP ECC errors.
Kindly note that I have already enabled ECC for flash region by setting ATCMPCEN bit in System control coprocessor’s Auxiliary control register, c1.
Please clarify my doubt whether ESM channel for flash ECC (TCM - ECC live lock detect) ESM group2 channel 16 will raise an error alarm for OTP ECC errors.
CPU accesses to Flash bank OTP regions, Flash ECC regions, and data Flash bank go through what is termed as the Flash Bus 2 interface. These memory regions are not mapped to the tightly-coupled memories for the CPU, and as such the CPU's ECC logic does not check ECC for accesses to these regions.
There is separate ECC logic inside the Flash interface module controller (called FMC in the TRM). This logic checks the ECC on accesses to the bus 2 interface and signals errors to the ESM. There is a table in the datasheet (table 6-36 on page 102 of SPNS162C) that lists all error sources, including those for accessing the Flash bus 2 interface.
Regards, Sunil
