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TM4C129ENCPDT: SS

Lukas Thumfart
Intellectual 275 points
Part Number: TM4C129ENCPDT


Dear Ti-community,

I have some issues to use the TM4C129 as SSI-slave. First of all, the master is sending two commands- and two crc- bytes with a baudrate of 1000000. Using a half full or mor RX interrupt is to slow to send back the data and the master detects errors. Polling with ssiget() and ignoring the crc is working but i dont want to use a blocking function.

Is there a way to act fast enough over SSI?

regards

Lukas

  • 0
    TI__Guru 72500 points

    Good question. Since the transfers are totally controlled by the master clock, the slave must have the data ready when the master sends a clock. If the master starts the clock to receive a response immediately (or very soon) after sending the second CRC byte, there may not be enough time to load the slave's transmit buffer with the response. If you don't need to read the second CRC byte before computing the response, try this. Before the transmission starts load the slaves TX FIFO with four bytes of dummy data (can be all 0's). Enable the slave's TX FIFO empty interrupt. When the master finishes sending the third byte, (the slave finishes sending the third dummy byte) the last byte in the TX FIFO will move to the TX buffer and the TX FIFO empty interrupt will be generated. You will have the time of the last CRC byte transfer (8 us) to service the interrupt and load the response into the slave's TX FIFO.

  • 0 in reply to Bob Crosby
    Guru 117855 points

    Once again - vendor agent provides an 'excellent analysis' - beneficial to 'poster yet (also) alien monitors...'

    Now w/that said - might 'gentle tweaks' - add to the 'richness' of vendor's method?    They (may) include:

    • Dummy data (all 0's) may also denote 'blocked and/or failed communication' - thus another (non-0 byte) *nearly guaranteed to NEVER Unwantedly ARISE' may be substituted.    (i.e. one byte - out of a mix of 256 - is removed from 'normal' use - yet ONLY that  unique byte - enjoys a 'singular & well recognized'  meaning!)
    • Promote the, 'TX FIFO Empty Interrupt' to 'HIGH & Preemptive' (i.e. VERY TOP Priority) just in case (other) interrupts are in play - & have launched earlier - and are 'in process.'    Slowing the SPI response!    (those (non SPI IRQs) will be (temporarily) 'Kicked to the Curb' - yet executed upon the SPI's Interrupt completion...)
    • Whenever such 'High Speed Robustness' is sought - communicating devices should be 'nearby' - and 'normal/customary' 'Transmission Line Like' pcb tactics (Short, Direct, Wide & Non-Via'ed pcb traces) should be employed...