TMDSRM48HDK: Exception Handling for FPU

See if this thread helps:

Regards, Sunil

Thanks, Sunil. It didn't help me.

I'm not using RTOS or UDIV assembly for the division. I'm sure the divide by zero is being executed because I see the DZC bit set in FPSCR when I execute the division. The disassembly shows:

 VLDR S0, [PC, #12]
 VLDR S2, [PC, #12]
 VDIV.F32 S1, S0, S2

In the example project that Jean-Marc provided from the thread you shared, why is the DZC bit in the Secondary Auxiliary Control Register being set with the code below?

 MRC p15, #0,r3,c1,c0,#0
 orr r3,r3,#0x80000
 MCR p15, #0,r3,c1,c0,#0

Since the DZC is bit 9, I expected a mask of 0x200 like below.

 MRC p15, #0,r3,c1,c0,#0
 orr r3,r3,#0x00200
 MCR p15, #0,r3,c1,c0,#0

Neither of the above set the DZC (bit 9) for me.

I enable the DZC bit with the code below and I see the DZC bit set as expected

        MRC   p15,     0,       r0,         c15,  c0,  0   r
        ORR   r0,      r0,      #0x000200    
        MCR   p15,     0,       r0,         c15,  c0,  0 

I'm not sure about c1 vs c15 but using c1 does not set the DZC bit.

Is my method of enabling the DZC bit correct?

Is there anything extra I need to do setting up VIM ch 47 as FIQ or IRQ.

I setup the VIM channel in vimInit() with

vimRAM->ISR[47] = (t_isrFuncPTR)&myFpuIntrHandler.

After vimInit() I enable interrupt with _enable_interrupt_()

Is there anything else?

Guy,

I only posted on that other thread to point out that the DZC enable control needs to be set in the c15 Secondary Auxiliary Control Register in order to let the FPSCR.DZC status flag cause an interrupt request to be generated. The Cortex R4/5 TRM includes example assembly instructions to read from and write to this register:

MRC p15, 0, <Rd>, c15, c0, 0 ; Read Secondary Auxiliary Control Register
MCR p15, 0, <Rd>, c15, c0, 0 ; Write Secondary Auxiliary Control Register

The Cortex TRM is what I followed to use my method (copied) below to write to the c15 register. This is essentially a read-modify-write so as you can see I read, modify with mask 0x200 (corresponding to bit 9 for DZC) and then write it back.

        MRC   p15,     0,       r0,         c15,  c0,  0 
        ORR   r0,      r0,      #0x000200    
        MCR   p15,     0,       r0,         c15,  c0,  0 

I'm sure the above works fine as I indicated in my previous post because I see the register bit enabled in my register window. I asked about Jean-Marc method because he addressed c1 register using a mask of 0x80000 and suggests that also enables the DZC bit.

So, let me clarify my question/situation:

I have enabled DZC exception with the assembly above.

I believe I have enabled interrupt in the RM48 with the steps I described previously.

I'm still not getting any interrupt when I divide zero which is why I'm asking if there is anything else to check.