TMS570LC4357: TMS570LC4357 - Questions from reviewing the device TRM

Responses 

1. Customer can run the LBIST test during startup, or can divide BIST into upto 24 intervals and running then during normal operation.If BIST is run during normal operation, SW needs to save the CPU content and reload them after BIST test.

   >> Built-In Self-Tests are not run automatically. They are always performed under the application's control. Self-tests on the CPU take it "offline" and require a CPU reset to resume normal operation, while self-tests on RAMs are destructive. Most applications choose to perform self-tests on power-up / down. These self-tests do need to be performed at least once every Multiple-Point Fault Detect Interval (MPFDI in ISO26262) in order to detect and address latent faults in the CPU/memories.

2. It is not required to use DMA. If they will transfer a big amount of data, using DMA is very beneficial as you said: making the CPU available for other tasks can lead to a big improvement in performance, data transferring and processing can be done simultaneously (real-time computing application). TMS570LS43x has 2 HW CRC modules.

   >> The Cortex-R4/5 CPU architecture is designed to execute as fast as possible from L1 (cache/TCM) memories. As designed, all peripherals are "far" from the CPU in terms of the number of cycles it takes to read from a peripheral, e.g. ADC conversion results RAM. The DMA is best used to transfer data from the peripherals to a memory "closer" to the CPU, so that the CPU does not waste precious time waiting for a read access to complete. The DMA does support multiple channels and has arbitration logic to ensure a single channel does not take up all the DMA bandwidth. So even if you have a DMA task for supporting a background CRC check of memories, it will still manage to share the DMA bandwidth for other transfers. Hercules parts' architecture is also designed to minimize the impact of DMA transfers on the CPU code execution.

3. There are three instances of temperature sensors in this microcontroller. The measured temperatures are analog signals. These analog signals are connected to the on-chip ADCs for conversion.

• Temperature sensor 1's output is multiplexed with AD1IN[31].
• Temperature sensor 2's output is multiplexed with AD2IN[31].
• Temperature sensor 3's output is multiplexed with AD2IN[30].
• AD2IN[31] and AD2IN[30] are not exposed on terminals but internally they exists and are used for temperature sensors.

4.  TMS570LC343x device has 32 DMA channels which can be assigned to any of the 48 HW DMA requests. The lower the channel number, the higher its priority. HW request assigned to the high priority DMA channel are always serviced first. There are 2 priority schemes: fixed priority and round-robin priority. Multi-thread transactions don’t happen at the same time.

5. MEM Swap: I am not sure it can improve the performance. There are some limitations to use the memory swap (swap mode). For example, you are not able to use all the flash memory since SRAM is only 512KB. The swap mode is normally used in debug mode where we can swap the flash and SRAM to load the code to SRAM and don’t not have to program the code to flash. The swap mode should not be used at run time. One of the draw back of swap mode is that the device will switch back to Normal mode (flash is at 0x0000_0000, SRAM is mapped to 0x0800_0000) in case of reset.

>> The memory swap between Flash and RAM was designed to allow developers to build code and test it without having to erase and reprogram the Flash memory. This is obviously limited to the available SRAM size, which is significantly smaller than the available Flash memory. Developers working on implementing a specific functionality (requiring smaller program memory) can use this feature. For actual application use cases, you can define functions that are used most often to be executed from RAM instead of Flash. This can be managed using the linker properties. See the ARM assembly language tools user's guide for more information: www.ti.com/.../spnu118

6. As stated in the paragraph, it is to minimize the runtime overhead for repeated correctable error at the same address. It doesn’t mean this memory implementation is more susceptible to this kind of error.

7. You are right, it is flexible. For protecting data, user runs their code in user mode. To switch to privileged mode, SVC or SWI should be used.

8. Is it clock domain or clock source? Which low power mode is used?

>> All clock domains are enabled upon wakeup. The clock sources to be used on wakeup depend on the G/H/V wake-up clock source configured.

9. RTI clock: the default clock source is VCLK. When device is in low power mode or the PLL is failed, RTI can use internal LPO clock as the clock source or can use OSCIN as the clock source.

>> Some low-power modes have been defined where-in the RTI module is kept active to provide periodic wakeups. In these cases, the RTICLK domain is switched over to a clock source that is also kept active through the low-power mode. All other clock sources and domains can then be disabled as part of the low-power mode.

10. The VIM module on TMS570LC43x supports 127 interrupt channels. Those interrupt can be configured as either IRQ or FIQ. All IRQ can be configured in either Register vectored mode or HW vectored mode. FIQ cannot be used as HW vectored mode. The total interrupt channels are not changed. Please refer to the interrupt channels in datasheet (Table 6-39)