TMS570LS0432: STC Test and Self-Test configurations

Dmitry Tuykov

Part Number: TMS570LS0432
Other Parts Discussed in Thread: HALCOGEN,

Hi TI team,

I'm working on STC tests implementation and faced with some questions regarding this functionality explanation within the TRM and implementation in HALCoGen. Hope you could help me with it.

If we look into code from HALCoGen, configuration for self-test (stcSelfCheck) is done in the following way:

stcREG->STCGCR0 = 0x00010001U;

So RS_CNT = 1 and INTCOUNT = 1.

But in accordance with the TRM (description of the STCSCSCR):

Self-check can only be done for the STC interval 0 by setting the RS_CNT bit in STCGCR0 to 1 to restart the self-test.

Question 1:

Which interval has to be select for self-test: 0 (TRM) or 1 (code)?

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If we look configuration for STC test (cpuSelfTest), its configuration is done as follows:

stcREG->STCGCR0 = no_of_intervals << 16U;
if(restart_test)
{
stcREG->STCGCR0 |= 0x00000001U;
}

Intervals are set as required, RS_CNT = 1.

If we look again to the TRM (description of the STCSCSCR):

To proceed with regular CPU self-test, STCSCSCR should be programmed to disable the self-check feature and clear the RS_CNT bit in STCGCR0 to 0.

Questions 2 and 3:

Which RS_CNT is desired for normal test (not STC self-test)?

What is the influence of this bit to the test execution? Description in the TRM is a bit unclear.

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Question 4:

Test implementation contains some delay loop before test enabling (for specific number of VBUS clock cycles). But I can't find the corresponding information within the TRM.

Could you give me a link, please?

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Question 5:

When self-test and STC test has to be executed: before clock configuration/after/does not matter?

Within the HALCoGen as I see, it is done after.

Thanks in advance for your help!

over 5 years ago

0 Sunil Oak over 5 years ago

TI__Mastermind 49120 points

Hello,

Sorry for the delay in getting back to you. See my comments in blue in the message below.

Question 1:

Which interval has to be select for self-test: 0 (TRM) or 1 (code)?

SRCGCR0 does not pick the interval number to be executed. It only configures the number of test intervals to be executed and whether the interval(s) to be executed need to restart from interval # 0. The last interval executed is captured in the STC Current Interval Count Register (STCCICR).

For self-test mode, code generated by HALCoGen always selects a single interval and always chooses to execute interval 0.

Questions 2 and 3:

Which RS_CNT is desired for normal test (not STC self-test)?

What is the influence of this bit to the test execution? Description in the TRM is a bit unclear.

The application must decide how much time it can afford to spend with the CPU running self-tests at a time. If it chooses to execute all available (26 in case of TMS570LS0432) STC test intervals at a time, then the RS_CNT configuration does not really matter.

Suppose the application chooses to execute a subset of the test intervals at a time, say 13, so that it wants to run the full CPU self-test in two separate runs at two different stages of the application. In this case, the first run would start from interval 0 (STCGCR0.RS_CNT = 1 and STCGCR0.INTCOUNT = 13).

The second run would then start with the 14th interval and run the remainder 13 test intervals.

Question 4:

Test implementation contains some delay loop before test enabling (for specific number of VBUS clock cycles). But I can't find the corresponding information within the TRM.

Could you give me a link, please?

I will have to look into this and get back to you on whether this delay loop is required or not.

Question 5:

When self-test and STC test has to be executed: before clock configuration/after/does not matter?

Within the HALCoGen as I see, it is done after.

You do want to run the CPU self-test at the maximum specified frequency. In case of TMS570LS0432 the max CPU clock frequency is 80MHz and the max STCCLK (divided down from CPU clock) is 45MHz. So you need to configure the clock domains such that the CPU clock is 80MHz and then the STCCLK is 40MHz (CPU clock / 2).

0 Dmitry Tuykov over 5 years ago in reply to Sunil Oak

Expert 1186 points

Hello,

thank you for your answer. Now it Is almost completely clear.

Open question is about delay before test running and one clarification, if you don't mind:

Questions 2 and 3:

Which RS_CNT is desired for normal test (not STC self-test)?

What is the influence of this bit to the test execution? Description in the TRM is a bit unclear.

The second run would then start with the 14th interval and run the remainder 13 test intervals.

As I understand, for the second run STCGCR0.RS_CNT has to be set to 0 to prevent test restart from the initial interval. Am I right?

Thanks in advance!

0 Sunil Oak over 5 years ago in reply to Dmitry Tuykov

TI__Mastermind 49120 points

Yes, the second run would need STCGCR0.RS_CNT = 0 to avoid starting over from interval # 0.

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TMS570LS0432: STC Test and Self-Test configurations