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CCS/RM48L952: CRC SEMI_CPU 64k limit

Part Number: RM48L952

Tool/software: Code Composer Studio

Hi,

I have a project where I want to check internal flash crc periodically in background.I tried the "RM48 CRC SW Full-CPU and Semi-CPU" example code, which is working until all linker section are below 64k.

When any linker section (.text, .const) is above 64k (crc->PCOUNT_REG1 >= 8192 with ACCESS_64_BIT), then crc->BUSY always returns with 1 and crc checking is stucks.

I didn't see any restrictions on this in the technical manual.

How can I solve this problem?

  • Hello Laszlo,

    Here you will find an example with PCOUNT = 1MB:

  • Hi Miro,

    Thanks for fast response.

    But that example is not working. 

    crc isn't configured to AUTO nor SEMI_AUTO mode. After crcInit() the module is in Full_cpu mode. Its running, but not working.

    In my sourcecode

    With TEST_FAIL define -> not working, Without TEST_FAIL define -> OK. Same problem occured when .text section is larger than 8192*64 bit. 
    Exactly when "sCrcParams.pcount>8191"

    Here is my sourcecode:


    #define TEST_FAIL #ifdef TEST_FAIL #pragma RETAIN(filler) const uint8 filler[65000u]={0}; #endif void mainTest(uint8 i) { crcInit(); dmaEnable(); /* Enable all interrupts for Channel 0 */ crcEnableNotification(crcREG, CRC_CH1_CC | CRC_CH1_FAIL | CRC_CH1_OR | CRC_CH1_UR | CRC_CH1_TO); crcConfig_t sCrcParams; g_dmaCTRL g_dmaCTRLPKT; /* Configure DMA Control Packed (structure is part of dma.c) */ g_dmaCTRLPKT.SADD = _my_crc_table.recs[i].addr; /* initial source address */ g_dmaCTRLPKT.DADD = (uint32_t)(&(crcREG->PSA_SIGREGL1)); /* initial destination address */ g_dmaCTRLPKT.CHCTRL = 0ul; /* channel control */ g_dmaCTRLPKT.RDSIZE = ACCESS_64_BIT; /* read size */ g_dmaCTRLPKT.WRSIZE = ACCESS_64_BIT; /* write size */ g_dmaCTRLPKT.FRCNT = 1; /* frame count */ g_dmaCTRLPKT.ELCNT = (_my_crc_table.recs[i].size + 7ul) / 8ul ; /* element count */ g_dmaCTRLPKT.ELSOFFSET = 0ul << g_dmaCTRLPKT.RDSIZE; /* element source offset */ g_dmaCTRLPKT.FRSOFFSET = 0ul << g_dmaCTRLPKT.RDSIZE; /* frame source offset */ g_dmaCTRLPKT.ELDOFFSET = 0ul << g_dmaCTRLPKT.WRSIZE; /* element destination offset */ g_dmaCTRLPKT.FRDOFFSET = 0ul << g_dmaCTRLPKT.WRSIZE; /* frame destination offset */ g_dmaCTRLPKT.PORTASGN = 4ul; /* only Port B */ g_dmaCTRLPKT.TTYPE = FRAME_TRANSFER; /* transfer type */ g_dmaCTRLPKT.ADDMODERD = ADDR_INC1; /* address mode read */ g_dmaCTRLPKT.ADDMODEWR = ADDR_FIXED; /* address mode write */ g_dmaCTRLPKT.AUTOINIT = AUTOINIT_OFF; /* autoinit off */ sCrcParams.crc_channel = CRC_CH1; sCrcParams.mode = CRC_SEMI_CPU; sCrcParams.pcount = g_dmaCTRLPKT.ELCNT ; sCrcParams.scount = 1u; sCrcParams.wdg_preload = 0u; sCrcParams.block_preload = 0u; crcChannelReset(crcREG, CRC_CH1); crcSetConfig(crcREG, &sCrcParams); /* Assign DMA Control Packet to Channel 0 */ dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT); /* Trigger DMA Channel 0 s/w request */ dmaSetChEnable(DMA_CH0, DMA_SW); while( (dmaREG->SWCHENAS & 1ul) | (crcREG->BUSY & 1ul) ) { /* Wait until DMA finsihed and CRC indicates block compressed */ } u64Signature = crcGetSectorSig(crcREG, CRC_CH1); /* Clear CH1_CCIT bit */ crcREG->STATUS = CRC_CH1_CC; /* Check CRC */ printf("mainTest CRC[%d]",i); if (u64Signature != _my_crc_table.recs[i].crc_value) { printf("Wrong @ address: 0x%08X\n", _my_crc_table.recs[i].addr); } else { printf("OK\r\n"); } } int main(void) { uint32 i; while (1) { for (i=0;i<_my_crc_table.num_recs;i++) { mainTest(i); } } }

    // #define TEST_FAIL
    #ifdef TEST_FAIL
    #pragma RETAIN(filler)
    const uint8 filler[65000u]={0};
    #endif

    int main(void)
    {
             uint32 i;

    while (1)
    {

    for (i=0;i<_my_crc_table.num_recs;i++)

      mainTest(i);

    }

    }

  • Hello,

    Sorry for the late reply. Do you have some progress on this issue?

  • Hello,

    Problem still existing, but I made a workaround for it. Workaround: Do not send any block that is larger than 8191 via DMA->CRC. 
    If block count is larger then 8191, split it to multiple iterations:

    1. init crc,
    2. reset crc channel,
    3. configure and send 8191 block with dma,
    4. wait for dma complete (do not reset crc),
    5. if any blocks remaining go to step 3.
    6. check crc complete
    7. read out crc value.

    If you have any other suggestions for it, please write it.

    Laszlo Koncseg