TMS570LC4357: LBIST test randomly fails on some HWs

Hello,

we have several HW designs with TMS570LC4357 and with only a single HW type we are seeing random LBIST failures (i.e. only few units of the same type fail, majority of the units work properly). The test fails with the following:

STCGSTAT=503h

STCFSTAT=3h

STCCICR=20002h

STCCADDR1=1EFh

STCCADDR2=1EFh

The self-test code looks as follows:

void stc1_launch(void)
{
  // Maximum STC clock is 110 MHz
  // Divide GCLK1 300 MHz by 3 to achieve this clock rate for both segments SEG0 and SEG1
  stcREG1->STCCLKDIV = STCCLKDIV_DIVSEG0_3 | STCCLKDIV_DIVSEG1_3;

  // Clear CPU RST status bit in the System Exception Status Register in the system module.
  // Note: Write 1 will clear this bit. Write 0 has no effect.
  systemREG1->SYSESR = Q_SYS_CPURST;

  // Configure the test interval count in STC module. Note that in case of multiple segments, segments run
  // sequentially, one after another depending on the number of intervals selected.
  stcREG1->STCGCR0 = (stcREG1->STCGCR0 & 0x0000FFFCu) | (U32)(STC_INTERVALS << 16u) | (U32)STCGCR0_RESTART;

  // Configure self-test run time out counter preload register
  stcREG1->STCTPR = 0xFFFFFFFFu;

  // Configure the STC to run both redundant CPU cores in parallel
  // The both CPU cores is default, but to be sure...
  do
  {
    stcREG1->STCGCR1 = 0x5u;
  } while((stcREG1->STCGCR1 & 0x00000F00u) != 0u);

  // Enable self-test controller
  stcREG1->STCGCR1 = 0xAu;

  // Put the CPU in idle mode to launch the self-test procedure
  // STC generates a CPU reset after completion of each test regardless of pass or fail
  for(;;)
  { __asm__ ("WFI"); }

  __builtin_unreachable();
}

and the evaluation code:

void stc1_checkResult(void)
{
  if((stcREG1->STCGSTAT & 0x2u) != 0u)
  {
    // Something is wrong with CPU logic => Generate system reset
    rtos_kprintf(RTOS_LOGLEVEL_FW_ERROR, "CPU/uSCU LBIST failed %Xh %Xh %Xh %Xh %Xh", stcREG1->STCGSTAT,
                                                                              stcREG1->STCFSTAT,
                                                                              stcREG1->STCCICR,
                                                                              stcREG1->STCCADDR,
                                                                              stcREG1->STCCADDR1);
    appReset(RST_TYPE_HOOK);
  }
  else
  {
    stcREG1->STCGSTAT = 0x1u; // Write 1 to clear TEST_DONE flag
  }
}

When STCCLK is set to 100 MHz, the test keeps failing, when we lower the frequency to 75 MHz, the problem is gone, and the test always passes.

Could you please recommend steps to find the root of the problem? Should we focus on a supply voltage? Is there some more detailed documentation (application note)?

Thanks in advance

  Jan Nárovec