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TMS570LS3137: MIBSPI parity check

Sankar P
Prodigy 210 points
Part Number: TMS570LS3137

Hi,

I have been trying to transmit data within the RAM using mibspi1 configuring itself as both master and slave externally without using loopback.

I have got the following queries:

When internal loopback is enabled, the data is transmitted from TXRAM to RXRAM through mibspi1, the parity bits are getting stored at the location 0xFF0E0400 after it is calculated by the controller.

After the transfer of data, the parity bits in location 0xFF0E0600 are updated with what they are stored in 0xFF0E0400. Is it calculated by controller or is the data transmitted?

The same functionality is observed even if the loopback test mode is disabled.

And when the loopback test mode is disabled, the parity bits are to be sent along with the data. How can we know that the parity bits are sent as those can't be accessible by the CPU as mentioned?

And, how can the receiver know that the parity is enabled when the data is sent?

When the data is received, where are the parity bits stored?

Please answer my queries.

Thanks,

Susvitha.

  • 0
    TI__Mastermind 27355 points

    Hello Susvitha,

    If the parity generator is enabled (can be selected individually for each buffer) an even or odd parity bit is transmitted at the end of a data word. During reception of the data word, the parity generator locally calculates the reference parity and compares it to the received parity bit.

    Please also see section 25.11 "Parity Memory" of the TRM.

    Regards,
    Sahin

  • 0 in reply to Sahin Okur
    Prodigy 190 points

    Hi Sahin,

    When an external interface is sending data to the controller TMS570LS3137, how will the receiving controller i.e. TM570LS3137 knows that the parity is enabled?

    Where can it be checked that the parity is enabled on the receiver side?

    Please answer this query.

    Thanks,

    Tirumala.

  • 0 in reply to Tirumala
    TI__Mastermind 27355 points

    Hello,

    There needs to be a common understanding between the master and slave on whether parity is enabled or not, similar to SPI clock phase/polarity, character length, etc. The parity bit needs to be calculated and transmitted by the sender and calculated/compared by the receiver.

    Regards,
    Sahin

  • 0 in reply to Sahin Okur
    Prodigy 210 points

    Hi, 

    Where are the parity bits stored in the sent and received data? How can they be accessed to check if the parity bits are sent or not? Can you please explain this.

    When the data is sent from the external transmitter, if the parity is disabled and then the parity will be zero. On the receiver side( suppose it to be the controller TMS570LS3137) the parity generator calculates the parity for the received data and it does not match with the bits received. The receiver will check the parity based on the common understanding between the master and slave. Is my understanding correct?

    Thanks,

    S Tirumala