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Correct method of stopping and restarting ePWMs

Jeremy Henderson
Intellectual 740 points


Hi Sunil, 

We are struggling with a slight issue still. The sampling is fine most of the time. However, we are double buffering the samples in order to process them while collecting more. So periodically we are stopping the ADC conversions, stopping the PWM, and re-configuring the DMAs to swap buffers, then restarting ADC conversions and finally restarting the PWM. We have seen instances where it appears as though the wrong ePWM SOC (SOCB) gets triggered first (and therefore the second DMA gets triggered first) and the buffered data is out of order (each pair of samples of the input AC waveform is swapped). When this occurs, it looks like two ePWM SOCs occur back to back. Is there a recommended method of stopping the ePWM SOCs and restarting them such that SOCA always occurs first?

We have tried freezing the PWM counter, then re-configuring the DMA buffers then setting the PWM counter to zero, then unfreezing it, but the issue persists.

  • 0
    TI__Mastermind 49120 points

    Jeremy,

    I have split this question from the earlier post to keep the topics separate. I will look into this tomorrow and get back to you.

  • 0
    TI__Mastermind 49120 points

    Jeremy,

    Can you post the code & sequence you are using to stop the ePWM and to restart it?

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Intellectual 740 points

    Hi Sunil,

    I am using the following code to stop the PWM SOCs:

    // Freeze the time-base counter
epwmReg->TBCTL.B.CTRMODE = 3U;

// Software-force the PWM output low
epwmReg->AQCSFRC.B.CSFA = 1U;
epwmReg->AQCSFRC.B.CSFB = 1U;

// Reset the current time based counter
epwmReg->TB       CTR = 0U;

    And the following code to restart it:

    // Remove Software forces
epwmReg->AQCSFRC.B.CSFA = 3U;
epwmReg->AQCSFRC.B.CSFB = 3U;

// Reset the current time based counter
epwmReg->TBCTR = 0U;

// un-freeze the time-base counter
epwmReg->TBCTL.B.CTRMODE = 0U;

    My team found that adding a 1us delay in-between stopping and starting the PWM resolves the issue, but we don't understand why. We also disabled the shadow mode for the software force and compare registers, I'm not sure if that's required or not, but we thought that having shadow mode enabled may create delays when restarting the PWM.

  • 0 in reply to Jeremy Henderson
    TI__Mastermind 49120 points

    Hi Jeremy,

    How do you identify that the SOCB is being generated before SOCA?

    There is a likelihood that the zeroing of the TBCTR is seen as a period match, which is the condition for generating SOCB. Some things (independent) to try and identify the issue here:

    • Clear the ETFLG SOCA and SOCB flags before restarting the counter?
    • Setup the TBCTR value to be 1 instead of 0 before restarting the counter?
    • Setup the counter to be in an up-down mode instead of an up-count mode?

    Regards, Sunil