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Hi Team,
Our customer has a minor clarification on TZ1n, TZ2n, TZ3n synchronization selection. Is the "6 VCLK3 Cycles Filter" a counter only output after 6 count with VCLK3 as input clock? If so, is the counter being counted up when TZnx is asserted and counted down when TZnx deasserted? Or is the counter reset to zero when TZnx is deasserted?
Thanks in advance for the help.
Kind Regards,
Jejomar
The filter is implemented such that any state transition that is shorter than 6 VCLK3 (+ 2 VCLK3) cycles is not seen as a valid transition.