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CCS/TMS570LS3137: Clarity about MIBSPI Parity check

Sankar P
Prodigy 210 points
Part Number: TMS570LS3137

Tool/software: Code Composer Studio

Hi,

When the data is transmitted using MIBSPI , there is a function mibspiParityCheck at the location 0x00001410. Can you please explain what is the purpose of the same.

Thanks,

Tirumala.

  • 0
    TI__Guru**** 196776 points

    Hello,

    The multi-buffer RAM contains a 4-bit parity field per word.

    Parity memory test mode is enabled and disabled by the PTESTEN bit in the UERRCTRL register. During the parity test mode, the parity locations are addressable at the address between RAM_BASE_ADDR + 0x400h and RAM_BASE_ADDR + 0x7FFh. Each location corresponds, sequentially, to each TXRAM word, then to each RXRAM word.

    During parity test mode, after writing the data/control portion of the RAM, the parity locations can be written with incorrect parity bits to intentionally cause parity errors.

    mibspiParityCheck() is to check if the parity diagnostic mechanism works as expected by injecting an fault.