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Compiler/TMS570LS3137: when the cpu is Self-checking,What is the status of the CPU

whong zhao
Genius 4180 points
Part Number: TMS570LS3137


Tool/software: TI C/C++ Compiler

 Hi

 TMS570LS3137 CPU is self-checking,  I see "SafeTI™ Hercules™ Diagnostic Library Release version 2.3.2"paper,some api spend more time.

 question:

 1.if cpu is self-checking ,Whether the interrupt function can execute.

2.The CPU self-test takes a long time, which will affect the operation of the entire program and the real-time response?

  Thanks

  

   

  • 0
    TI__Guru**** 198766 points

    Hello,

    1. No, the CPU core master bus transaction signals are configured to be in idle mode during the self-test tun.

    2. You can run the STC test during startup or can divide STC into 24 or fewer intervals and run them during normal operation. If STC is divided into intervals and ran, user software must save the CPU contents and reload them after the CPU reset caused by the completion of the STC test interval.

    It only takes 1365 clock cycles (15.17 us at VCLK=90MHz) for each test interval.

  • 0 in reply to QJ Wang
    Genius 4180 points

    Thank you 

    During the self-test tun,cpu can't do anything ,which is very scary thing.

    what does this means, take long time?

     

  • 0 in reply to QJ Wang
    Genius 4180 points

    Thank you 

    During the self-test tun,cpu can't do anything ,which is very scary thing.

    what does this means, take long time?

     

  • 0 in reply to whong zhao
    Genius 4180 points

    Hello

     I want to know this api function ..""

      when those api function run,can the cpu  run the other interrupt function?

  • 0 in reply to whong zhao
    TI__Guru**** 198766 points

    Hello,

    The PBIST is usually run on device start-up as it is a destructive test and all contents of the tested SRAM module are overwritten during the test. 

    During CPU selftest, the CPU core is completely isolated from the rest of the system. After CPU selftest, the STC generates a CPU reset regardless of pass of fail of the test. 

    CPU will not handle the interrupts during those 2 selftests.