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TMS570LS3137-EP: How to disable unused registers

Part Number: TMS570LS3137-EP
Other Parts Discussed in Thread: HALCOGEN

TMS570LS3137-EP
HalcoGen 4.07.00
CCS 8.1.0.00011

Hello,

First I would like to say that I am not sure the best way to word my question(s), so please bear with me.

Our customer requires us to document that unused registers are disabled or at least do not cause negative side effects. For example, we are not using LIN or FlexRay. How do I disable these? (If that even makes sense)

In _c_int00 a function of sys_startup.c file, function memoryInit is called that enables DMA, VIM, CAN, ADC and that memoryInit function is in sys_selftest.c file. LIN and FlexRay are not listed in the argument flags. Does this mean that LIN and FlexRay are never enabled, therefore they are disabled?

I had a hard time trying to search for this information in the spnu449c document. I just need something that I can point to that says something along the lines “If the registers were never enabled, they are disabled by default”.

If there is a function similar to memoryInit that I can point to and state “the flags for these items were never set, they are disabled” that works too.

Apologies for the long wordy question. Please let me know if you need any other info.

Regards,
Ryan

  • Hello Ryan,

    There are 3 ways of disabling a module:

    1. through PMM: you can power down a power domain (PD2, PD3, PD4, PD5) through PMM registers

    2. through PCR: to disable the peripheral through PSPPwrDwnSet[x] register. Each peripheral select (PS) addresses a 1KB region. This region is then divided into four quadrants [3 - 0], with each quadrant being 256 bytes. These quadrants are then assigned to individual peripheral module control/status registers. Some peripheral register frames fit within a quadrant, while some other peripherals take two quadrants. Please refer to PCR section in TRM.

    https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/785547/2905699?tisearch=e2e-sitesearch&keymatch=PSPWRDWN#2905699

    3. through the module registers if available. for example DCAN module can be locally powered down by setting PDR bit in DCAN control register. Please refer to "24.12.1 Entering Local Power Down Mode" in DCAN chapter

  • Hello QJ,

    Thank you for getting back to me. that is big help. i will let you know if i run into any issues.
    Sorry the late reply got side tracked on something else and now that is "more important".

    Thanks again,
    Ryan

  • All table, section and page references are from spnu449c.pdf unless otherwise noted.

    Hey QJ,

    I am back on this again and was able to get the PMM items turned off. Thank you for that. Now, I am working on the PCR power down. My first question is:

    In Table 2-3 (pages 104-108): What does "unimplemented" mean in "RESPONSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME"
    Does "unimplemented" mean powered down via PMM or PCR, or does it mean their init function was never called, or both?

    I did look at the link you provided regarding power down Peripherals using the PCR and I am unclear on how to set the Protection registers. Is that required if I am going to power them off?

    Finally, I assume if I can power down both the Peripheral Memory and Registers I should do so? (for example MIBSPI5, pages 105 and 107)

    Regards,
    Ryan

  • Hi Ryan,

    1. Unimplemented ..: The memory location is not actually there. For example, the frame size of NHET1 RAM (0xFF46_0000~0xFF47_FFFF) is 128KB, but the actual size in this device is only 16KB (0xFF46_0000 ~ 0xFF46_0400). The address above the highest real memory (0xFF46_0400) is not implemented.

    2. The PCR PPROTSETx and PMPROTSETx registers protect the peripheral registers and memories against illegal writes by the CPU. The CPU can read from the peripheral registers and memories in both user and privileged modes. There is no access protection for real operation. 

    The PCR module PMPROTSETx registers contain one bit per peripheral memory frame (PCS[x] in table 2-3). 

    The PCR module PPROTSETx registers contain one bit per peripheral select quadrant. These bits define the access permissions to the peripheral register frames (PS[x] in Table 2-3). 

    If you are going to power off a module, it doesn't matter to set the protect registers or not.

    3. PCSPWRDWNSET[x]: only one bit for one peripheral memory. MibSPI5 RAM is  #5 (PCS[5] in table 2-3). Setting bit 5 of PCSPWRDWNSET[0] will power down this module memory.

        PSPWRDWNSET[x] is to power down the peripheral and was mentioned before. 

  • Hi QJ,

    1. Unimplemented: That makes sense. I was looking at the Peripheral Control Register section, where the Frame Size and Actual Size match, I think that is what confused me. 

    2. Protection: In that case, I am not going to set this if I am power it down. 

    3. PCSPWRDWNSET[x]: I have gone through and powered down the peripheral registers and associated memory if applicable.

    Thank you for your feedback.

    New: 

    After powering off the items I wanted (like MibSPI5) I noticed that when I ran with the debugger, the MibSpip5 registers were not all zeros. Maybe they dont need to be, but i assumed they would be if the memory and registers were powered off. Here are a few of the ones that are set:

    IntFlg: 0x0100_0000 - BUF Init Active (buffer is being initialized)

    DIn (Pin Control 2): 0x0F0F_0F0F - basically initializing pin direction and enabling

    PSel (Pin Control 8): 0x0F0F_0F0F 

    RxBuf: 0x8000_0000 - no data received

    Emu: 0x8000_0000 - reserved

    DefCs: 0x0000_000F - no transfer active

    Overall it seems like these are default values. Is it ok that the registers contain values even though they powered down? (Are these values correct/expected?) 

    Best,
    Ryan 

  • Hello Ryan,

    "Implemented" doesn't apply to the case that the frame size is equal to actual size.

    To clarify, the PSPWRDWN and PCSPWRDWNSET bits in the PCR are to put a module into a state of reset. In this case the clocks will be gated to these modules and they will not be clocked. However, if the CPU makes an access to them, they will be temporarily clocked for the singular access but then gated again after the access. The specific point I wanted to clarify is that these bits do not disable the clock domains which are enabled/disabled via the clock domain set and clear registers.

    So you can read the default value back even the module (MibSPI5) is powered down through PCSPWRDWNx and PSPWRDWNx registers.