RM48L952: RM48L952 read/write SDRAM has problem

Simon Lin1

Part Number: RM48L952

Dear Sirs,

SDRAM : Alliance AS4C32M16SB-7TIN , 8M word x 16-bit x 4-bank.

EMIF_CLK : 44MHz

Problem : When I write a 16 bit data at one odd address, the whole SDRAM looks to be written that data. And when I write data at even address, it seems not write any data. The uKEIL C memory window display the result. I also read the data at different address after last write. The result is same as memory window displayed.

My configuration for SDRAM has 3 parts:

1. clock : please refer my system.c.

2. pin connection : please refer my pinmux.c.

3. emif_SDRAMInit( ) : please refer my emif.c.

read / write code :

volatile uint16 *ptr = ((volatile uint16 *)0x80000000U);
uint16 aaa[10];

.....

while(1)
{
*ptr = (uint16)0x1234;
*(ptr+1) = (uint16)0x5678;
*(ptr+2) = (uint16)0x9ABC;
*(ptr+3) = (uint16)0xDEF0;
*(ptr+4) = (uint16)0x2233;
*(ptr+5) = (uint16)0x4455;
*(ptr+6) = (uint16)0x6677;
*(ptr+7) = (uint16)0x8899;

aaa[0] = *ptr;
aaa[1] = *(ptr+1);
aaa[2] = *(ptr+2);
aaa[3] = *(ptr+3);
aaa[4] = *(ptr+4);
aaa[5] = *(ptr+5);
aaa[6] = *(ptr+2);
aaa[7] = *(ptr+3);
}

Maybe I configure wrong or miss some important setting. Could anyone help me to figure out the problem. Thank you so much.

6320.system.c

8865.emif.c 6663.pinmux.c

over 5 years ago

0 QJ Wang over 5 years ago

TI__Guru**** 196816 points

Hello Simon,

The tXSR=tRC+tIS=63+1.5=65.

I use the parameters listed in Table 16 of AS4C32M datasheet, and got different EMIF settinfs:

/* SourceId : EMIF_SourceId_001 */
/* DesignId : EMIF_DesignId_001 */
/* Requirements: HL_SR334 */
void emif_SDRAM_StartupInit(void)
{
/* USER CODE BEGIN (11) */
/* USER CODE END */

volatile uint32 buffer;

/* Procedure B Step 1: EMIF Clock Frequency is assumed to be configured in the startup */

/* Procedure B Step 2: Program SDTIMR and SDSRETR to satisfy requirements of SDRAM Device */
emifREG->SDTIMR = (uint32)((uint32)2U << 27U)|
(uint32)((uint32)0U << 24U)|
(uint32)((uint32)0U << 23U)|
(uint32)((uint32)0U << 20U)|
(uint32)((uint32)0U << 19U)|
(uint32)((uint32)0U << 16U)|
(uint32)((uint32)1U << 12U)|
(uint32)((uint32)2U << 8U)|
(uint32)((uint32)0U << 7U)|
(uint32)((uint32)0U << 4U)|
(uint32)((uint32)0U << 3U);

emifREG->SDSRETR = (uint32)2U;

/* Procedure B Step 3: Program the RR Field of SDRCR to provide 200us of initialization time */
emifREG->SDRCR = 8000005U;

/* Procedure B Step 4: Program SDRCR to Trigger Initialization Sequence */
/** -general clearing of register
* -for NM for setting 16 bit data bus
* -cas latency
* -BIT11_9CLOCK to allow the cl field to be written
* -selecting the banks
* -setting the pagesize
*/
emifREG->SDCR = (uint32)((uint32)0U << 31U)|
(uint32)((uint32)1U << 14U)|
(uint32)((uint32)2U << 9U)|
(uint32)((uint32)1U << 8U)|
(uint32)((uint32)2U << 4U)|
(uint32)((uint32)elements_256);

/* Procedure B Step 5: Read of SDRAM memory location causes processor to wait until SDRAM Initialization completes */
buffer = *PTR;
/* prevents optimization */
buffer = buffer;

/* Procedure B Step 6: Program the RR field to the default Refresh Interval of the SDRAM*/
emifREG->SDRCR = 1343U;

/* Place the EMIF in Self Refresh Mode For Clock Change */
/* Must only write to the upper byte of the SDCR to avoid */
/* a second intiialization sequence */
/* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */
*((unsigned char *)(&emifREG->SDCR) + 0x0U) = 0x80U;

/* USER CODE BEGIN (12) */
/* USER CODE END */
}

0 Simon Lin1 over 5 years ago in reply to QJ Wang

Prodigy 80 points

Hello QJ,

Thanks for your help. I tried your EMIF init code and got the same result as before. The SDRAM is written same value at every address when I just write one value at one odd address.

Best Regards,

Simon Lin.

5482.emif.c

0 QJ Wang over 5 years ago in reply to Simon Lin1

TI__Guru**** 196816 points

Hello Simon,

This is the snapshot of my test on TI RM48 HDK using your code. But I use different parameters since the SDRAM on HDK is different from yours:

0 QJ Wang over 5 years ago in reply to QJ Wang

TI__Guru**** 196816 points

Tried the same parameters used in your setup, SDRAM on HDK still works as expected.

I noticed that you use 8192 as the refresh cycles in your emif.c. Normally the refresh cycles of a SDRAM is 4096, please double check the SDRAM datasheet.

0 Simon Lin1 over 5 years ago in reply to QJ Wang

Prodigy 80 points

Hi QJ，

Yes, I run my SDRAM code on HERCULES, it can r/w the SDRAM on HERCULES board correctly. When I change the generated code to myself sdram and run it on my board, the issue appears.

My input parameters are as following: