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Original question:

Compiler/TMS570LC4357-EP: Regarding HCLK on TMS570LC4357

Compiler/TMS570LC4357-EP: N2HET function

Given Ding
Genius 10165 points
Part Number: TMS570LC4357-EP

Tool/software: TI C/C++ Compiler

Hi Team,

Here is a question on use of N2HET. 

when writing command to data field , CPU is also reading this data field, what will happen?  

Also, when cache is enabled in CPU, is there abnormal issue when writing or reading data field in N2HET, is there need to take special care in code? 

Thanks. 

BRs

Given 

  • 0
    TI__Guru**** 197306 points

    Hello Given,

    CPU can make updates to the N2HET RAM while the N2HET is executing, for example to update the duty cycle value of a PWM, it is important to understand how the N2HET RAM organization facilitates simultaneous accesses by both the HOST CPU and the N2HET.


    The N2HET RAM is implemented as 4 banks of 96-bit wide two port RAM. This means that there a total of 8 ports available; four read and four write. Normally the N2HET will use up to two of these ports at a time. One read port is used to allow the N2HET to prefetch the next N2HET instruction while a write port may be used to update the data or control fields that have changed as a result of executing the current instruction.


    N2HET accesses to its own internal RAM are given priority over accesses from an external host (CPU or DMA), this makes N2HET program execution deterministic which is a critical requirement for a timer.

    The cache does not affect the reading from NHET RAM, but it affect if the read data is updated in CPU SRAM.

  • 0 in reply to QJ Wang
    TI__Genius 10165 points

    Hi QJ,

    Thanks for your reply.

    customer understand that N2HET has priority over CPU but still feel confused on the behavior of CPU when there is conflict. when CPU is reading RAM at same address, after one execution, it moves forward. So what's the value it will read when there is conflict?

    also, for the effect that cache may have, what does code need to do ? Thanks.

    BRs

    Given

  • 0 in reply to Given Ding
    TI__Guru**** 197306 points

    Hello Given,

    1. When CPU reads from an N2HET instruction while the N2HET is executing from/on the same address or same bank, the CPU will be stalled for one cycle. 

    Assuming most of the N2HET program executes linearly through the N2HET address space, if a bank conflict does exist it is usually resolved in the next cycle as the N2HET program moves to the next bank.

    N2HET programmers should avoid writing a program that accesses the same bank of N2HET RAM on every cycle, as this could lock the external host out of the N2HET memory completely.

    2. If the value reading from N2HET memory is not shared with other masters (for example DMA, EMAC, etc), the cache setting should not cause any issue, so you can use either write-through or write-back. If the value is shared with DMA, you have to configure the SRAM region (used for this value) as write-through.