• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 284 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS570LC4357: External SRAM/ECC and Fault Signaling

TMS570LC4357: soft-error detection on external SDRAM

Eric_Song_
Prodigy 20 points
Part Number: TMS570LC4357


Hi,

I have a similar question.

The safety goal is DC 90%.

We aim to have external 16M SDRAM.

I agree if there is only data in the external SDRAM, we can use CRC to have an end-to-end protection.

But what if there are instructions running in SDRAM, when there is soft-error in the SDRAM to make some bits of SDRAM incorrect...

Do you have some good advices on how to make DC of that part achieve 90%?

  • 0
    TI__Mastermind 49120 points

    Hi,

    The LC4357 does not have a built-in method to determine if there is a fault in the SDRAM itself. You can create write-read-compare methods using software to test SDRAM locations for hard errors. Soft errors are very hard to catch even with this method.