• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 31 subscribers
  • Views 345 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/RM48L952: Flash Uncorrectable Error Address - Value Reset Capability

Mux
Intellectual 620 points
Part Number: RM48L952


Tool/software: Code Composer Studio

Hello TI,

I have a question regarding the Flash Uncorrectable Error Address Register (FUNC_ERR_ADD) when I generate an error on purpose on one of the main flash banks (bank0 and bank1) in order to trigger the ECC event detection which will capture the address in that specific register. As I am injecting this error on purpose (e.g. at the startup) to test the ECC hardware detection on the flash banks, I would like to know if there is a mechanism to clear the value and keep it to "0" when the "real" application starts to execute after the testing procedures.

On the one hand the TRM says:

"During emulation mode, this address is frozen even when read. By setting the SUSP_IGNR bit, this register can be unfrozen in emulation mode. This register is not changed with the reset signal and contains unknown data at power-up."

But on the other hand, it doesn't state anything if its possible to clear the value.

If it is possible to do so, are there specific steps to reconsider (e.g. can be done in privileged mode only,etc.)

  • 0
    TI__Guru**** 198766 points

    Hello,

    For flash error detection status register (FEDACSTATUS), all error status bits can be cleared by writing a 1 to the bit. Writing a 0 has no effect.

    Flash uncorrectable error address register is not changed with the reset signal, register read/write, even power-on reset. This register can be cleared. 

  • 0 in reply to QJ Wang
    Intellectual 620 points

    Hello QJ Wang,

    the information for the FEDACSTATUS register is clear for me as it is documented in the TRM.

    For the FUNC_ERR_ADD, is it possible to clear the value as your second statement in your post, gives the impression that you cannot do so. Nevertheless, at the end you say it is possible to clear the value.

    So what is the current conclusion out of this and if possible how can I apply it /clear the value during startup tests in order to test the ECC event mechanism of the chip. 

  • 0 in reply to Mux
    Intellectual 620 points

    Hello QJ Wang,

    any information on this topic from diagnostic perspective?

  • 0 in reply to Mux
    TI__Guru**** 198766 points

    This register cannot be cleared. sorry for my typo.