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EK-TM4C1294XL: Address/Data Bus Endian

Victor L-S
Intellectual 925 points
Part Number: EK-TM4C1294XL

Hello,

I have been using the EK-TM4C1294XL for prototyping generic Flash memory readers. In the past the Flash had been written to by a Intel 80C198 microcontroller. The current Flash has been written to by a Freescale MPC5554 which has the address and data lines reversed to that of the TM4C1294XL. My simple solution was to do the reversing as shown in the attached PCB design with U4 and U5 driving the address bus while U6 handles the data bus.

My question is...Is there a more elegant hardware solution to the one I have chose?

Thank you for your assistance,

Victor

  • 0
    TI__Guru**** 191296 points

    Hi Victor,

      The TM4C129 processor is little-endianism. I can't decipher from your layout. I assume you are doing byte swapping before reading the data - meaning swapping between Byte0 and Byte4 and between Byte 1 and Byte2. Is that correct?  That should be the correct way to handle data endianism conversion. You should be able to handle the swapping in software too. Have you tried that? Swap the bytes before you process the data. This should work if you are reading data from the external flash, not running code out of the external flash. 

  • 0
    Guru 117855 points

    Greetings,

    Victor L-S said:
    Is there a more elegant hardware solution to the one I have chose?

    How is "elegant" to be defined?    Cannot "elegance" exist in:

    • financial return
    • top performance
    • ease of use
    • size reduction
    • speed of development
    • adding additional features - raising value
    • and multiple, other factors

    Somehow a reasonably small FPGA - coupled w/a low pin-count ARM M0 - appear to offer the best combination of, "Flexibility & Adaptive Capability."

    Adequate definition really would assist your, "application's satisfaction."      We are told that, "Like beauty - elegance often lies in the eye of the beholder..."

  • 0 in reply to Charles Tsai
    Intellectual 925 points

    Hello Charles,

    An MPC5554 was used to write the data to the Flash through its EBI (External Bus Interface) which specifies the following...

    MPC 55xx / 56xx are natively Big-endian devices as well as most of Freescale devices. However Power Architecture uses numbering style that bits in registers and address lines on external bus are marked in reverse.

    EBI line with highest number (dependent on data bus width – A31 for 8bit bus, A30 16bit bus and A29 for 32bit bus) is connected to memory LSB address line, then downwards according to size of connected memory.
    So your SRAM connection will be EBI_ADR[30:x] -> SRAM_ADR[0:y]
    DATA0 is most significant bit, and DATA31 is least significant bit.
    ADDR0 is most significant bit, and ADDR31 is least significant bit.

    This is also indicated by the connection schematic shown below. The MPC5554 EBI A30 is connected to memory pin 31/A0. EBI A05 to pin 55/A25. Similarly the data bus is reversed. The connector to the memory is laid out in EBI format. What my layout shows is the reversing of the EK-TM4C1294XL bus just before the connector to account for the reversal. 

    I guess my unsolvable question is...is there a chip out there when given an LSB D0/MSB D15 input produces an LSB D15/MSB D0 output. Similarly given an LSB A0/MSB A25 input produces an LSB A30/MSB A05 output.

    Thank you for your time,

    Victor

  • 0 in reply to Victor L-S
    TI__Guru**** 191296 points

    Hi Victor,

      I'm not familiar with Freescale's MPC processor. It is the first time I have come across that a bit swap is needed rather than byte swap. I will suggest you contact Freescale support for suggestions on what chips to do the swapping. I won't be surprised there are people asking this type of questions to Freescale. I have you have tested your current solution - swapping them on your schematic as an alternative solution.