RM46L852: Nand Flash ECC check at boot

Hello,

When flash ECC is enabled, all accesses to the program flash memory are protected by SECDED logic embedded inside the CPU. The data that is read from the f;ash is always the same as the data that had been written to it, even if one of the bits actually stored has been flipped to the wrong state. 

ECC evaluation is done by the ECC control logic inside the CPU. Detected uncorrectable errors result in a processor abort or bus error depending on the requesting master. Detected correctable errors can be corrected or not corrected, depending on whether correction functionality is enabled. The address of the memory, which includes the ECC error, is logged in the CPU.

1. The ECC logic for the Flash is disabled at reset and must be configured in both the CPU and the Flash wrapper.

/* Enable CPU ECC checking for ATCM (flash accesses) */
_coreEnableFlashEcc_();

2. To export error detection events from the CPU to the Flash wrapper, and then from the Flash wrapper to the ESM.

/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();

/* Enable response to ECC errors indicated by CPU for accesses to flash */

flashWREG->FEDACCTRL1 = 0x000A060AU;

3. Do diagnostic test to make sure the ECC logic works properly.

/* Test the CPU ECC mechanism for Flash accesses.
* The checkFlashECC function uses the flash interface module's diagnostic mode 7
* to create single-bit and double-bit errors in CPU accesses to the flash. A double-bit
* error on reading from flash causes a data abort exception.
* The data abort handler is written to look for deliberately caused exception and
* to return the code execution to the instruction following the one that was aborted.
*
*/
checkFlashECC();

All those code in blue are generated through HALCoGen (sys_startup.c)