Part Number: TMS570LC4357
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Part Number: TMS570LC4357
Hello,
If cache is enabled, the cache is clocked by GCLK (no waitstates).
For SRAM, it is clocked by HCLK and is limited to maximum 150 MHz, and data waitstates = 0.
For Flash, L2 flash is clocked by HCLK and is limited to maximum 150 MHz, and waitstates = 0~3. The flash can support zero data wait state up to 45 MHz.
.