Hi,
Background:
In the TRM on the SCR Control Module (SCM), section 3.3.2 "How to Initiate Self-test Sequence", it states "3. Software needs to ensure that all bus master connecting to the interconnect should stop sending new transaction to interconnect."
When I check the register SCMIASTAT to determine if there are still pending transaction for the corresponding master, the 12th bit is set to 1. The 12th bit is the CPU PP-AXI.
What I have tried:
1. I read in the TRM, in secion 2.4.3.1, that "when a WFI instruction is executed, the Cortex-R5F core flushes its pipeline, flushes all write buffers and completes all pending bus transactions". So I thought, if I performed a WFI instruction, it would clear the 12th bit of the SCMIASTAT register. The WFI instruction did not clear the 12th bit.
2. I also tried to see if SCMIASTAT is cleared prior to the call to main. I was thinking that if you execute before main, there are no bus transactions taking place yet. But SCMIASTAT register bit 12 is still set to 1.
Is there another way to ensure all bus transactions are completed and SCMIASTAT register is set to 0x00000000?
Thanks,
JC
