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TMS570LC4357: NMPU lockstep feature / Registers called in SNPU563A

Stephan HERMANNS
Intellectual 590 points

Part Number: TMS570LC4357

Hello, Team of TI support,

My question is regarding the Technical Reference Manual (TRM) SPNU563A belonging to the TMS570LC4357.
In section 11.2.3.1 a bit DIAGERR is called that should be contained in register MPUERRSTAT.

In whole chapter 11 "System Memory Protection Unit (NMPU)" I cannot find a detailed description of the DIAGERR bit,
particularly not in section 11.4.5.

So my questions are:

(Q1) Is a lockstep feature comparing a Primary block and a Checker Block available in the three NMPUs of the TMS570LC4357?

(Q2) If so, where may I find a detailed description of this lockstep feature and the DIAGERR bit called?

Thank you in advance for your support.
Stephan

  • 0
    TI__Guru**** 199346 points

    Hello Stephan,

    I am in travel, and will reply you as soon as I can. 

  • 0 in reply to QJ Wang
    Intellectual 590 points

    Hello QJ,

    Hope You enjoyed your trip.

    Did you already have an opportunity to think about my questions in this thread as well as my questions in thread 879796?

    Enjoy the day!

    Stephan

  • 0 in reply to Stephan HERMANNS
    TI__Guru**** 199346 points

    Hello Stephan,

    I am sorry for late reply.

    The lockstep is implemented for address masking, address translation, and mode translation. If there is a lockstep comparison error, the ERRFLG in MPUERRSTAT register will be set. But DIAGERR is not implemented. The fault insertion is also not implemented.

  • 0 in reply to QJ Wang
    Intellectual 590 points

    Good morning, QJ,

    I would like to thank you for your answers. I have four more questions - three of them have rised up by your answers.

    (Q3) Which ESM Error occurs when ERRFLAG is set?

    (Q4) Is "address masking" another term for "address decoding"?

    (Q5) I do not understand the meaning of "address translation" in the scope of a NMPU - i would associate that function rather with a MMU that with a MPU.

    (Q6) Does "mode translation" mean that the originating access mode of the bus master is rewritten by the value of MPUREGACR? If so, is this also true for the DMA bus master which access mode is "user mode" as stated in section 20.2, sentence 5, of the /TechRef/: "All DMA memory and register accesses are performed in user mode"?

    Thanks again - i'm looking forward your supporting answers.