Hello, Team of TI support,
My question is regarding the Safety Manual (SM) SPNU540A belonging to the TMS570LC4357.
In sections 6.11, 7.61 and in row "MEM3" in table 4 of the above document, the safety measure "Information Redundancy"
is called as a diagnostics for the CPU Interconnect Subsystem (SCR).
We are wondering to see a SW-based diagnostics on such a basic functionality like accessing the Primary SRAM.
Our thoughts have been that in a product (SEooC) certified for implementing SIL 3-rated functions the
HW-based diagnostics provided are sufficient to ensure a proper detection of random HW faults particularly
for functions located in the Safe Island region.
Our question is:
(Q1) How is the means "Information redundancy" (MEM3) motivated to be used on Safe Island functions, i.e.
under which circumstances the above means should be used?
I appreciate your efforts in advance
Stephan
